Article View: comp.lang.prolog
Article #22Prolog compilers for RISC architectures
From: Tong Bo-Ming
Date: Thu, 29 Oct 1992 09:13
Date: Thu, 29 Oct 1992 09:13
7 lines
787 bytes
787 bytes
Is it possible for Prolog compilers to take advantage of the large number of registers in RISC architectures ? If the compiler is WAM-based, this seems very difficult. Are there any register allocation schemes which can get around this problem ? Tong Bo-Ming bmtong@cs.cuhk.hk
Technical Details
Message-ID:
<1992Oct29.091339.20207@cucs5.cs.cuhk.hk>Path:
arc1-ca.pugleaf.net!sparky!uunet!cis.ohio-state.edu!zaphod.mps.ohio-state.edu!saimiri.primate.wisc.edu!uakari.primate.wisc.edu!hp9000.csc.cuhk.hk!cucs5.cs.cuhk.hk!bmtongShow Full Headers
Complete Article Headers
Newsgroups: comp.lang.prolog Path: arc1-ca.pugleaf.net!sparky!uunet!cis.ohio-state.edu!zaphod.mps.ohio-state.edu!saimiri.primate.wisc.edu!uakari.primate.wisc.edu!hp9000.csc.cuhk.hk!cucs5.cs.cuhk.hk!bmtong From: bmtong@cucs11.cs.cuhk.hk (Tong Bo-Ming) Subject: Prolog compilers for RISC architectures Message-ID: <1992Oct29.091339.20207@cucs5.cs.cuhk.hk> Sender: news@cucs5.cs.cuhk.hk Organization: Faculty of Engineering, The Chinese U. of Hong Kong Date: Thu, 29 Oct 1992 09:13:39 GMT Lines: 7