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Article #29

Re: Prolog compilers for RISC architectures

#29
From: Andrew Taylor
Date: Fri, 30 Oct 1992 20:49
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In article <1992Oct29.091339.20207@cucs5.cs.cuhk.hk> bmtong@cucs11.cs.cuhk.hk (Tong Bo-Ming) writes:
>Is it possible for Prolog compilers to take advantage of the large number
>of registers in RISC architectures ?  If the compiler is WAM-based, this
>seems very difficult.  Are there any register allocation schemes which
>can get around this problem ?

Inter-procedural(predicate) register allocation is one way to soak
up excess registers. This can be applied in a native code Prolog compiler
just has been done with imperative languages.

You must take garbage collection into account.  Many garbage collectors
need to know which registers are valid at the program point at which they
have been invoked. This requires passing information describing the "global"
registers. The alternative is to use a robust garbage collector
but this (I think) would require all stack words to be tagged.

I can't see the point in extending the WAM do this but it might be useful
in a native code global analysis-based Prolog compiler (see papers by me or by
Peter van Roy).

Andrew Taylor
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From: andrewt@watson.ibm.com (Andrew Taylor)
Newsgroups: comp.lang.prolog
Subject: Re: Prolog compilers for RISC architectures
Message-ID: <1992Oct30.204952.92247@watson.ibm.com>
Date: 30 Oct 92 20:49:52 GMT
References: <1992Oct29.091339.20207@cucs5.cs.cuhk.hk>
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