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Article #4356

FGCS'92 Workshop on Parallel Programming and Architecture

#4356
From: Ueda Kazunori
Date: Tue, 24 Mar 1992 14:34
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         --- Second Announcement and Call for Participation ---

                    Workshop on Future Directions of
                 Parallel Programming and Architecture
                              June 6, 1992
                     Shiba Park Hotel, Tokyo, Japan

                          in conjunction with
                      International Conference on
                 Fifth Generation Computer Systems 1992
                             June 1-5, 1992


The workshop is intended to assess the status of those questions central
to the FGCS conference, and set a new set of goals.  In particular, we
would like to address the following questions:

  1. What have been our major technical successes over the past decade?
  2. What major challenges remain to be overcome before we can achieve
     an unqualified success? (and how does one define success?)
  3. Which goals must be reached if we take on these challenges?

In supporting the answers to these questions, we would like to review
the various areas of parallel programming and architecture.  The topics
include, but are not limited to:

  o Parallel logic programming languages,
  o Parallel execution models,
  o Compilation techniques (type and mode inference, optimization)
  o Parallel implementations,
  o Programming environments (debugging, performance tuning, visualization)
  o Mapping (load balancing, scheduling, communication),
  o Massively parallel and data parallel computation, and
  o Parallel architectures.

We would like to run this workshop along the lines of a working-group
(rather than a "show and tell") with focused discussions and some
concrete results -- refreshed views of our broad research area.

WORKSHOP ATTENDANCE AND PAPER SUBMISSIONS:

Due to space limitations and the need to provide better interaction, the
number of attendees is limited to 40.  If you are interested in
attending, e-mail a 2-8 page extended abstract or a 1-page position
paper to the following address by March 31:

     Jiro Tanaka
     IIAS-SIS, Fujitsu Laboratories
     1-17-25 Shinkamata, Ota-ku
     Tokyo 144, Japan
     e-mail: jiro@iias.flab.fujitsu.co.jp
     fax:   +81-3-3730-6830

Emphasis is on the abstract which includes one's own view and prospect
on the above mentioned topics.  Include your address, e-mail address and
work telephone number in your abstract.

Submissions will be reviewed by the workshop organizers.  Higher
priority is given to extended abstracts that clearly cover the authors'
views on the above three questions (in any of the suggested or other
relevant areas).  Authors will be notified of acceptance or rejection by
April 19.  Informal proceedings will be compiled.  The final copy for
inclusion in the proceedings must be received by May 15.  All questions
regarding the workshop should be directed to the organizers.

IMPORTANT DATES:
     Deadline for abstract/position paper submission:  March 31
     Notification of acceptance:                       April 19
     Final copy for inclusion in the proceedings:      May 15

WORKSHOP ORGANIZERS:
     Jiro Tanaka, Fujitsu Laboratories, Japan (Chair)
     Jonus Barklund, Uppsala University, Sweden
     Doug DeGroot, Texas Instruments, USA
     Nobuyuki Ichiyoshi, ICOT, Japan
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From: ueda@icot31.icot.or.jp (Ueda Kazunori)
Newsgroups: comp.lang.prolog,fj.meetings
Subject: FGCS'92 Workshop on Parallel Programming and Architecture
Message-ID: <1992Mar24.143453.5203@ss151.icot.or.jp>
Date: 24 Mar 92 14:34:53 GMT
References: <1992Mar24.142816.5019@ss151.icot.or.jp>
Sender: news@ss151.icot.or.jp
Organization: ICOT, Tokyo, Japan
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