🚀 go-pugleaf

In article <1991Apr2.214724.9835@oakhill.sps.mot.com>,
bryant@oakhill.sps.mot.com (Bryant Wilder) writes:
> in our group we use silicon compiler system tools' M modeling 
> language for our high level chip block simulations.  we would
> like to use synopsys inc.'s logic simulation tool also, but 
> synopsis only supports VHDL at the present time.  does anyone
> have any experience with both M and VHDL who would care to 
> comment openly or privately about how to make VHDL communicate
> with M.              
> 
M is a superset of C.  VHDL is, well, VHDL.  You would have a much easier
time coverting your M models to Verilog, which incidently, Synopsys DOES
support.  Motorola has Verilog in their ASIC divisions, so you may be able
to use one of their licences. 

I couldn't tell from your posting if the goel is to:
a) Use Synopsys, and convert your models into something that Synopsys supports,
b) Use VHDL, then you can use Synopsys,
c) Quickly convert your models into something that is Synopsys-ible, or
d) Ability to synthesis your design.

If a), Synopsys supports both VHDL and Verilog.  Evaluate both.
If b), then buy VHDL.
If c), Verilog may be your best bet since it looks more like M.
If d), Motorola should get its act together and pick one simulator.  Again,
if your are an experienced M user, Verilog would enjoy a much shorter learning
curve.  Then you can still use Synopsys OR you can evaluate Cadence's new
synthesis tool.

Also, Synopsys wants to use RTL-level models, not behavioral, since
commercial synthesis technology is net yet at the level of synthesising
behavioral code (I assume that when you said "high-level...simulations",
you meant at the behavioral level).  So, you would have to do a fair amount
of rewriting anyways to convert from behavioral to RTL.

Therefore, there is no good mechanical conversion technique since you want to:
1) Change languages, and
2) Change levels

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