🚀 go-pugleaf

I would appreciate comments from experienced VHDL users on how to 
estimate the effort required in writing VHDL behavioral models. The 
models I have in mind would be detailed enough to provide the
correct function at the module I/O pins so that tests written for the 
behavioral model could also be run on the structural VHDL model for
the same module to be written later.

For example, how much effort would be required to write a model for
a module with the following characteristics?

200K gates of logic including a 1750 cpu and 5 ASICs, several memories
and some buffers.

Also, how should timing and set-up and hold checks be included in 
the behavioral model?

thanks,
Bruce Grugett
Harris GASD
407-727-5017