🚀 go-pugleaf

I've just started using ports of mode BUFFER in a model, and there are
a few things that aren't making sense.  Consider the following
architecture:

Architecture A1 of E1 Is
    Signal s1: Bit_Vector(1 to 2);

    Component Driver
        Port(b1, b2: Buffer Bit);
    End Component;
Begin
    D1: Driver
        Port Map(s1(1), s1(2));
End A1;

Is this model legal?  When I analyze it (using Vantage), it complains
that s1 has more than one source, apparently counting the two ports as
separate sources of s1 as a whole (and an actual of a Buffer port may have
at most one source).  LRM Sec. 4.3.1.2 indicates that, for a resolved
signal at least, the two ports would "together constitute one source of
the signal."  What is the rule for unresolved signals (note that, if
the two ports do constitute one source, there is no need for s1 to be
resolved, since there are no other sources).

While we're on the subject, why can't actuals of buffer ports have
more than one source (and please don't say "Because!")?  I had
previously assumed that a buffer port would act as, well, a buffer,
isolating the signal value inside the component from the effects of
external drivers (as opposed to an INOUT port, where the internal value
would be the same as the effective external value).  Given that the
actual only has one source, how does a BUFFER port differ from an
INOUT port?
-----
John A. Breen 				|  johnb@hobbes.mdc.com
McDonnell Douglas Missile Systems Co.	|  jab0396@cec1.wustl.edu (forwarded ^)
Tel: (314)234-4341