🚀 go-pugleaf

I am having some problems with VHDL.  Basically, sometimes it
differentiates between a constant, a variable, and a signal.  Other
times it does not.  For example:

PACKAGE stats IS
  -----------------------------------------------------------------------------
  --  TrackUtilization accumulates the utilization of the indicated component
  -----------------------------------------------------------------------------
  PROCEDURE  TrackUtilization  (CONSTANT inst  : IN STRING;
                               VARIABLE delay : IN REAL);
END stats;

ENTITY sounds IS
  GENERIC ( INST: STRING := "_bark" );
  PORT    ( inval : IN REAL );
END sounds;


USE work.stats.ALL;
ARCHITECTURE moo OF sounds IS
  CONSTANT meow   : REAL := 2.0;

BEGIN

  MooProc : PROCESS (inval)
    VARIABLE oink   : REAL := 1.0;
    VARIABLE myname : STRING ( 1 TO 13 )  := ("Animal Sounds");
  BEGIN
    TrackUtilization  (INST, oink);   -- will work fine
    TrackUtilization  (INST, meow);   -- won't, since meow is a constant.
    TrackUtilization  (INST, inval);  -- won't, since inval is a signal (port).
    TrackUtilization  (myname, oink); -- won't, since myname is a
                                      -- variable.
  END PROCESS MooProc;

END moo;


--  So, sez I, since I can't do that (being that the Powers hath decided
--  that such implicit overloading on IN parameters is not a Goodly thing),
--  I'll just overload TrackUtilization:


PACKAGE new_stats IS

  -----------------------------------------------------------------------------
  --  TrackUtilization accumulates the utilization of the indicated component
  -----------------------------------------------------------------------------
  PROCEDURE  TrackUtilization  (CONSTANT inst  : IN STRING;
                               VARIABLE delay : IN REAL);
  PROCEDURE  TrackUtilization  (VARIABLE inst  : IN STRING;
                               VARIABLE delay : IN REAL);
  PROCEDURE  TrackUtilization  (CONSTANT inst  : IN STRING;
                               SIGNAL delay : IN REAL);
  PROCEDURE  TrackUtilization  (CONSTANT inst  : IN STRING;
                               CONSTANT delay : IN REAL);
END new_stats;



But the compiler barfs whilst complaining about homophobic (graphic?  Same
difference :) declarations.  Which seems kind of strange - it makes the
distinction earlier, but now it cannot tell the difference.  Is this VHDL?  Or
the specific VHDL intrepretation which we are using?  I could probably be
convinced that overloading a SIGNAL on a VARIABLE for an INOUT or an OUT
parameter might not be a good idea, but for an IN parameter?  What difference
could it make?  And if you force me to suffer with that, why can't I then
overload the procedure calls?