🚀 go-pugleaf

In article <3200@ucl-cs.uucp> you write:
>
>I believe there is a group (VHDL Synthesis Working Group in Europe???) that
>is trying to specify this subset.
>
If you are interested in writing portable VHDL then a subset of
the syntax is not very useful. The most important area were
the synthesis tools differ is in the interpretation of semantics.

For example we are using Mentor's AutoLogic and working with customers
who have Racal and Synopsys.  The Racal user doesn't think our VHDL
will synthesise well on SilcSyn because it doesn't do resource
sharing and so the same (large) adder would be built separately
for each decode in the controlling state machine. AutoLogic builds
a single adder cells and multiplexes the input where needed.  They've
also found nested IF's don't give good results on Racal so avoid
using them.  We've never had that sort of problem and use netsted
IF's all the time.

Even clock recognition is not simple. We have described clocks
as IEEE 1164 9-state logic and used the syntax:-
   IF clk = '1' AND clk'LAST_VALUE = '0' AND clk'EVENT THEN
This tells AutoLogic the clock has changed and is a rising edge.
Unfortunately when our customer tried to compile it under Synopsys
he had to remove the 'LAST_VALUE test. OK using 'LAST_VALUE is pedantic 
but logically more correct since a 'X' to '1' transition is not a rising
edge and so without the 'LAST_VALUE test there could be differences
between a VHDL simulation and synthesised logic's behaviour when
a 'X'-->'1' vector is applied to a clock.

There are also incompatibilities in the way arithmetic is interpreted.
Should bit level values be magnitude or 2's complement? How do you
define overflow in arithmetic operations? A VHDL simulator will
report a run-time error on overflow but the synthesised logic can't!
Would the logic wrap around through zero, reset or go to some
random undefined value?

The good news is Synopsys, Mentor and Viewlogic are supposed to
be working together on a unified arithmetic library for the IEEE
1164 logic type ( the IEEE only defined logical operations on the
type).  I just hope its not too diferent from the arithmetic which
Mentor have already implemented! 

Roger Knight                   rknight@gec-rl.hrc.co.uk
VHDL ASIC Design Group
Hirst Research Centre,
GEC-Marconi Ltd.

DISCLAIMER: I said it not my company.If any of the above is bu****t,
misleading or just plain wrong - thats your problem not mine.