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Article #345Re: Conversion of Verilog timing checks to VHDL?
From: Gautam Singh, Graduate Student (...
Date: Fri, 18 Dec 1992 10:27
Date: Fri, 18 Dec 1992 10:27
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I don't believe there are standard functions for doing this. However, you can quickly write your own functions (they will be typically constitute of a line or two) using the signal attributes such as SIGNAL'DELAY, SIGNAL'ACTIVE, SIGNAL'EVENT, and similar other attributes. If you have trouble doing that, contact me through e-mail, and I can mail back these functions to you.
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Newsgroups: comp.lang.vhdl Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!caen!destroyer!wsu-cs!falcon!gsingh From: gsingh@eng.wayne.edu (Gautam Singh, Graduate Student (ECE), 577-4725) Subject: Re: Conversion of Verilog timing checks to VHDL? Message-ID: <1992Dec18.102741.29354@cs.wayne.edu> Sender: usenet@cs.wayne.edu (Usenet News) Reply-To: gsingh@eng.wayne.edu Organization: College of Engineering, Wayne State University, Detroit Michigan, USA References: <dank.724653378@blacks.jpl.nasa.gov> Date: Fri, 18 Dec 1992 10:27:41 GMT Lines: 7