🚀 go-pugleaf

Hopefully this will not appear twice - I previously
posted it to the wrong news category.

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I am looking at the EIA/IEEE logic modeling packages.

I am a little confused, since I thought that there would
be only one resultant package that both agreed upon.  I
have two apparently different VHDL packages:  One from
Len Finegold (EIA) and one from Victor Berman/W. Billowitch
(IEEE).  They are different.  I have not examined them in great
detail, since I am not sure whether the intent is to have only
one package eventually.

I am wondering if anyone out there has an answer to the questions:

	- is one a subset of the other?
	- are they compatible but different internally?
	- what supporting stuff is safe to use with both?

The point is that if they are not the same, and have different
supporting packages (e.g. TIME_FUNCS), then it is unclear which
one is the industry standard.  It is also unclear which supporting
code will work with which package.

Thanks for any help on this.

I am sending a copy of this note to Finegold and Billowitch.

Ray Voith   rayv@revenge.sps.mot.com   512-891-2265