🚀 go-pugleaf

In article <C16JE5.6tp@utdallas.edu> clarkw@utdallas.edu (WILLIAM D CLARK) writes:
>
>I would like to ask for suggestions or experiences from those of you
>who have used either or both of these simulators.  All comments (good
>or bad) are welcome.  
>
>BTW -- the reason we believe our choice should be between these two is
>that we will be using Synopsys' Design Compiler for synthesis and
>Mentor's GDT IC tools for layout and schematic capture (if needed).
>We believe our interfacing problems will be minimized by using one of
>these two.  


If you've already decided on Mentor's schematic editor then you would probably
do well to limit your choices to Mentor and Synopsys.  However, if you're
not limited to their schematic editor, then you might wish to look at Viewlogic's
new VHDL simulator.  The Synopsys->Viewlogic path is very good, better than
the Synopsys->Mentor.  Viewlogic also has the advantage of having just aquired
Vantage Systems, who supposedly have the best _compiled_ VHDL simulator.

Andy Frazer