🚀 go-pugleaf

> Is there any options in the vhdl language that lets me declare types
> equivalent to the "union" in C. The brute force method that I can think of
> is to declare a record with all the possible choices in the original union
> as a strictly present field; and have integer tags to access the types: 
> ...

No.  There are no variant record types in VHDL.  Sorry.  

Your workaround is the best solution I know of if you need to declare signals
or constants of that type.  If you're working with variables only (e.g., in
one process), you can declare a record containing pointers to different types,
and then allocate data for only the type that's used.

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Daniel S. Barclay                    --who's still searching for a good 
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