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This is a monthly posting to comp.lang.vhdl containing general informations
Please send additional information directly to the editor:
    dettmer@ls1.informatik.uni-dortmund.de (Thomas Dettmer)
Last edited: december 1992 (Thanks for all corrections)
corrections and suggestions are appreciated.
There are other regular postings about books, tools and conference dates.

Contents
0. General Information/Introduction
1. Abbreviations
2. Official Contacts
3. frequently asked questions

There are now other monthly postings containing informations about
products, books
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0. General Information/Introduction
The Group
The newsgroup comp.lang.vhdl was created in January 1991. It's an
international forum to discuss ALL topics related to the language VHDL which
is actually defined by the IEEE Standard 1076/87. 
Included are language problems, tools that only support
subsets etc. NOT other languages such as Verilog HDL. This is not strict -
if there is the need to discuss information exchange from EDIF to VHDL for
example, this is a topic of the group. The group is unmoderated. Please
think carefully before posting - it costs a lot of money! (Take a look into
your LRM for example - if you still cannot find the answer, post your
question, but make sure, that other readers will get the point).
A chapter for frequently asked questions about the language will later be
added to this regularly posted information - as they appear on the net. If
necessary for the amount of information, this posting will possibly be split
into separate postings for each chapter.

VHDL
VHDL-1076 (VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language) is an IEEE Standard since 1987. It is "a formal notation intended
for use in all phases of the creation of electronic systems. ... it supports
the development, verification, synthesis, and testing of hardware designs,
the communication of hardware design data ..." [Preface to the IEEE Standard
VHDL Language Reference Manual] and especially simulation of hardware
descriptions. Additionally VHDL-models are a DoD requirement for vendors.

Today simulation systems and other tools (synthesis, verification and others)
based on VHDL are available. The VHDL users community is growing fast. 
Several international conferences organized by the VHDL Users Groups(s) have
been held with relevant interest. Other international conferences address the
topic with growing interest as well (Conference on Hardware Description
Languages -CHDL-, [European] Design Automation Conference -[Euro]DAC ...).

Changes to VHDL: A revised version of the language will
become the official IEEE standard in the near future. 
According to IEEE rules this can happen all 5 years. 
Changes include: groups, private types, shared variables,
inclusion of foreign models in a VHDL description, shift operators, support
of pulse rejection by a modified delay model, more syntactic consistency.
First adopted tools are expected in winter 1993/4 -correct me if I'm wrong.

Before posting
- read this article - it possibly answers your questions
- question about the language: try to find out in your LRM

1. Abbreviations

BBS: 	Bulletin Board System
DoD: 	USA Department of Defense
IEEE: 	The Institute of Electrical and Electronics Engineers
	In case of VHDL, they defined the standard 1076
LRM:	Language Reference Manual
TISSS: 	Tester Independent Support Software System 
VHDL: 	VHSIC Hardware Description Language
VHSIC: 	Very High Speed Integrated Circuits - A program of the DoD
VUG: 	VHDL User's group. See below.
VIUF:	VHDL International Users Forum
WAVES:  Waveform Vector and Exchange Specification, proposed IEEE Standard

2. Official Contacts

VHDL User's group. VHDL International Users Forum
    The first (VUG) was transformed into the second in 1991.
    VIUF is Chaired by Larry Saunders and is sponsored VHDL
    International(VI) They organize conferences, send a newsletter (paper)
    and have some other activities.
        Points of contact are:
        Larry Saunders, Chairman of VIUF 507 285 9547
           lfs@mcimail.com
         North Oaks EDA Consulting
         6472 North Oaks Court N.E.
         Rochester MN 55904
        Michael Carroll, Chief of VI 415 329 9570
    European Contact:
        Andreas Hohl
        SIEMENS, Dept. ZFE IS EA Ref
        Otto-Hahn-Ring 6
        8000 Munich 83
        Germany
        Phone: +49-89-636-41895
        Fax:   +49-89-636-44950
        Email: ah@ztivax.siemens.com

VHDL Newsletter
    Editor of the US Newsletter:
    Rachael Rusting
        Phone +1 617 661 1840, FAX +1 617 868-2843
        email: rmr@inmet.inmet.com
    Fred Hinchcliffe
        Phone: (301) 963-5200
  Europe
    Editor of the European Newsletter
        J. Mermet, J. Rouillard
	Phone: 3+91 05 44 44, FAX 33+91 05 43 43
	Institut Mediterraneen de Technologie
	Technopole de Chateau-Gombert
	13415 Marseille cedex -FRANCE-

mailing list/ftp addresses
    Mail items of interest to info-vhdl@uceng.uc.edu. (the last newsletter
    said VHDL@uceng.uc.edu ??)
    Mail a request to be added to the group of registered news subscribers
    to info-vhdl-request@uceng.uc.edu. 
    One can access the files online by "ftp"ing to account
    anonymous@uceng.uc.edu. 
    WAVES/TISSS infos account anonymous@tisss.rl.af.mil,
    is anonymous@131.5.15.3 - actually has problems

This posting
    Thomas Dettmer, University of Dortmund, Dept. of Computer Science I
    Box 50 05 00
    W-4600 Dortmund 50 (Germany)
    Phone: +49-231 755 4825,  FAX: +49-231 755 2386
    email: dettmer@ls1.informatik.uni-dortmund.de


3. frequently asked questions
There's not much until today - but I included those questions I've often
heard from beginners. (only one today)

USE of library elements?
Often users believe, they can use names of libraries /= work by simply
inserting a use clause in the source. The analyzer responds with error
messages.
Insert a library clause before the use clause and all
should work fine. (See your LRM for details).

PUBLIC DOMAIN?
Actually as far as I know, there is only few PD software on VHDL. If YOU
know about something, please let us know. 
See products posting for more detailed information.

VHDL Validation Suite available?
YES. free for universities and $2000 for companies and governmental agencies.
see monthly posting on products.

tom

-- 
dettmer@ls1.informatik.uni-dortmund.de
phone: +49-231 755 6323, FAX: +49-231 755 6555
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germany