🚀 go-pugleaf

This is a monthly posting to comp.lang.vhdl
Please send additional information directly to the editor:
dettmer@ls1.informatik.uni-dortmund.de (Thomas Dettmer)
Last edited: december, 1992 (Thanks for all updates and corrections)

Corrections and suggestions are appreciated. If I lost some, please forgive
me and send it to me again.

This product list is never up to date it seems - please help to update it.
This list is without any guarantee to be complete or correct. It is included
to enable contacts to vendors. It does not contain version, quality or price
information.  (Please accept, that actually this information changes to fast
-too much work to keep such information up to date, but if there is a
volunteer willing to take this part...:-). 
If some kind of judgement is included ('specialist' for example) it's not my
personal opinion but a remark from the vendor himself.

In the european VHDL newsletter I found a list of products not included in
this list - possibly someone can give more information to include it in this
list? At least I'm missing adresses. They are:
product		who	what
Amical		INPG	synthesis
		Bull	formal verification
Prevail		ARTEMIS	formal verification
		IKOS	grph. interface & simulation
SYNT/MINT	Synthesia synthesis/simulation
TransGATE	TransEDA synthesis/optimisation

********************* Special products and PD stuff ***********************
VHDL Validation Suite                 Oct 15th, 1990
           VHDL VALIDATION SUITE RELEASE ANNOUNCEMENT
  The  VHDL  Validation Suite, which was developed at Va. Tech
  with  funding  provided  by  CAD  Language   Systems   Inc.,
  Daisy/Cadnetix,   Genrad,  MCC,  Silicon  Compiler  Systems,
  Vantage Analysis, and Zycad is now ready for public release.
  The suite contains 2295 tests which cover 100% of  the  1865
  test  points defined for the VHDL Language Reference Manual.
  The suite is free to universities.   Companies  and  govern-
  mental  agencies  are required to pay a fee of $2000 for the
  suite. The funds from these fees will be  deposited  in  the
  VHDL  Suite  Foundation account and will be used to maintain
  and improve the suite.
  The suite is written in: 1) TAR format on Sun/Appollo  cartridges,
  or 2) DEC VMS BACKUP format on TK50 cartridges.
  To obtain a copy of the suite send :1) ei-
  ther a TK 50 (specify whether you want TAR or BACKUP format)
  or Sun/Appollo cartridge and 2) a check  (not  required  for
  universities) for $2000, made out to VHDL Suite, to:
         Professor J. R. Armstrong
         Bradley Department of Electrical Engineering
         Virginia Tech
         Blacksburg, VA. 24061
  If you have questions, contact Dr. Armstrong at 703-231-4723
  (phone),   703-231-3362   (FAX)   or   by   email   sent  to
  JRA@VTVM1.BITNET.

Proposed IEEE VHDL Standard Logic System: available via anonymous ftp
from bears.ece.ucsb.edu. The file is now called std_logic_1164.vhdl.
Ignore zero length file comp.lang.vhdl (internal remarker).
The correct path is now /pub/VHDL/comp.lang.vhdl
There is an automatic service that will mail the contents on request: Find
out how to use it by mailing the message "HELP" to BITFTP@PUCC.BITNET or
BITFTP@PUCC.Princeton.edu.

A Public Domain VHDL Parser/Generator written in Prolog
is available via anonymous FTP from the Microelectronics
Center of North Carolina (MCNC.ORG). Look for vhdl.tar.Z in /pub
For a more up-to-date version of this software (including
bug fixes, a graphical editor and logic synthesis modules),
contact Peter Reintjes at Quintus Corporation:
NEW email adresses!!:
     pbr@quintus.com         (they are on the internet now!)
or   pbr@deerfeld.ingr.com   (I work for DASIX now!)
Readers comment: This seems to be mcnc.mcnc.org. I successfully ftp'd into
the site 

A vhdl program has been developed which reads a
subset of the VHDL language and allows structural
descriptions to be elaborated and converted into
misc netlist formats. Currently supported are
1) EDIF 2 0 0 : edif netlist is generated for use with cadence ic layout
tools, specifically place and route. Attributes are used to store tool
dependent informationa 
2) VHDL : VHDL is read in and a simplified VHDL structural netlist
(flattened, only BIT types) is output. This is used to create vhdl
description for program using a smaller VHDL subset.
3) XILINX XNF format :
4) SILOS netlist     : under development
Some simulation capabilities are available in this program.
Currently only enough to allow simulation of standard cells
in a structural description. This will soon be extended.
This program is still in an early form, and contains plenty of bugs.
To obtain a copy : anonymous ftp to ftp.ee.umanitoba.ca (130.179.8.1)
change directory to  vhdl, file vhdl_1_1_3.tar.Z contains vhdl program
If you do not have anonymous ftp access, mail to: blight@ee.umanitoba.ca
For more info contact : Bob Mcleod mcleod@ee.umanitoba.ca or David C Blight,
University of Manitoba, Dept of Electrical and Computer Engineering,
blight@ee.umanitoba.ca

Package for "Analog and Mixed Analog-Digital Design Using VHDL", written by
Bernt Arbegard, Radiosystems Sweden AB. By anonymous ftp from swedish
institute of microelectronics: ftp.inmic.se (192.16.125.90) in dircetory
vhdl.

A VAL/VHDL to VHDL translator: available via anonymous ftp from
wilbur.stanford.edu [36.14.0.30] in the directory /pub/val.  Both
source code and binaries are available.  It is written in Ada, and
includes a full VHDL parser, with extensions for VAL.  Binaries are
available for Sequent Symmetry, Sun3, and Sun4.  Contact: Larry M.
Augustin, lma@dayton.stanford.edu.

I don't know if the following tools are PD or not, but they are accessible
    uceng: :there is a grammar suited for lex, but no actions
associated.  There is also a validation suite.
(anonymous FTP on uceng.uc.edu)

******************* Companies and their products ************************
Ascent Technology, Inc. 
Readers Note: name changed; now VLT
2075 North Capitol Avenue, Suite C
San Jose, CA 95132
phone:  (408) 945-6635, fax:    (408) 946-0922
contact: Rindert Schutten
 MetaView : basic design environment to be customized
 VHDL/DA :  Design Assistant (VHDL/DA) : MetaView based environment
           for design management, structure editing, browsing, state
           machine editing, architecture editing source code 
           transformation ( for synthesis )
********************************************************************
CAD Language Systems, Inc.
USA:
 5457 Twin Knolls Road, Suite 101
 Columbia, MD 21045
 Phone: (410) 992-5700
 Fax:   (410) 992-3536
 Email: support@clsi.COM
Japan:
 Shunsuke Miyakushi
 Bussan Electronic Systems Technology, Inc.
 Sanseido Building
 4-15-3 Nishi-Shin-Juku
 Shin Juku-Ku, Tokyo /60, Japan
 Phone: +81 3 3374 1161
 Fax:   +81 3 3374 9450
Europe:
 (Please contact USA)
Products:
 VTIP    - VHDL Tool Integration Platform: this is a VHDL analyzer,
           a VHDL generator, and an intermediate form database with 
           a procedural interface. Full 1076-1987.
 RVCG    - Retargetable VHDL Code Generator: generates C code for
           use in VHDL simulation using the VTIP. Allows integration of
           VHDL simulation with existing (or new) simulators.
 VMT     - VHDL Modelling Tool: a compiled code simulation system based
           on the RVCG, high-performance kernel, and Motif interface.
 VFormal - Formally verifies the equivalence or non-equivalence
           of VHDL designs with respect to their specifications.
 A program for training, university&research program
********************************************************************
Cadence Design Systems, Inc.
Systems Division
Two Lowell Research Ctr. Dr.
Lowell, MA 01852-4995
FAX 508-441-1109
OR
555 River Oaks Pkwy.
San Jose, Calif. 95134
Eileen Elam (Public relations representative)
(408) 943-1234
Germany:
Mr. Grothe
phone: 02236 68051
 Vdoc  Verilog to VHDL translator
 VHDL-XL simulator
Valid (part of CADENCE now)
2820 Orchard Pkwy.
San Jose, Calif. 95134
Germany:
Muenchen,
phone: 089/710050
 compiler, simulator
 Now sells Intermetrics tools
********************************************************************
Computer General Electronic Design Ltd.
 Contact: Arthur Burnley, Sales Manager
 Computer General Electronic Design Ltd
 5 Greenways Business Park
 Bellinger Close
 Chippenham
 Wiltshire
 SN15 1BN
 U.K.
 phone:+44 249 445566  Fax:+44 249 445595
 e-mail:arthur@cged.co.uk
Specialists in VHDL design, synthesis, simulation and test.
Products/services include:
- VHDL Design Station.  Design capture, synthesis, simulation workstation
          including: ECS Schematic capture, LOCAM synthesis, CLSI VHDL
Modelling
          kit.  Basic configuration inc. SparcStation costs UK L19,950.
-       CLSI's VHDL Modelling Kit (distributor), low cost, interactive, VHDL
          compiler and simulator 
- LOCAM including VSyn, fast, memory efficient synthesis for structural, d
ataflow
          and behavioral VHDL 
-       OPTIMA, retiming synthesis tool, which adds/removes pipelining and
          dramatically improves the results of logic synthesis for area,
timing 
and power
-       Panther Test synthesis which may be integrated in synthesis flow
          from VHDL
-       The ELLA HDL/ASIC design environment / behavioural simulator
-       ELLA -> VHDL translator
-       VHDL and ASIC Design Services

********************************************************************
Daisy/Cadnetix
    DAZIX, An Intergraph Company (attention: new name and address)
    USA
200 Caspian Drive
Sunnyvale, CA  94088
contact: Michael Yang
Phone: (415)691-9680  Fax: (408)747-7854

EUROPE

Germany: Cologne (49)221 89 1038
	 Munich (49)89 92 69 060
	 Stuttgart (49)711 728 9078
France:  Paris (33)1-4537 7100
United Kingdom: Newbury (44)635 550 455
Italy:   Milano (39)39 637 251
Netherlands: Breda (31)76 71 5200
Sweden:	 Sollentuna (46)8-920740
Norway:	 Billingstadsletta (47)2-84 82 40
Finland: Espoo (358)0-455-4744
Spain:	 Madrid (34)1-372-8017
Switzerland: Urdorf (41)1734 1920

ASIA/PACIFIC

Japan:	 Tokyo (81)3 345 77 501
Korea:	 Seoul (82)2 738 7441
Hong Kong: Wanchai (852)866 1966
Singapore: (65)73 452 88

PRODUCTS

VHDL Design System: IEEE VHDL 1076/87 compliant VHDL design and simulation 
environment with syntax-driven editor, source-level debugger, and waveform
analysis.
VHDL Export System: IEEE VHDL 1076/87 compliant VHDL source code generation
tool from existing schematic and libraries for DoD required documentation.
********************************************************************
i LOGIX
22 Third Av.
Burlington, MA 01803
Tel. 617 272-8090
Fax. 617 272-8035
 EXPRESSV-HDL, a graphical behavioral modeling tool allows
 hardware engineers to design with the precise graphical language of
 STATECHARTS- a powerful extension of state transition diagrams.
 Designers can create behavioral and functional models of
 circuits, analyze the design using the simulation and dynamic
 analysis capabilities proving that the design is correct before
 code generation. EXPRESSV-HDL then automatically generates 
 VHDL and VERILOG from the models both of which are fully compatable 
 with industry leading HDL simulation and synthesis tools.
********************************************************************
Intermetrics 
Intermetrics:
   Phone: (703) 827-2606
   FAX:   (703) 827-2609
   Addr:  7918 Jones Branch Drive, Suite 710
          McLean, VA  22102
 VHDL Design Environment	simulation system SUN/DEC
 University Program
Readers note:  no longer has any commercial VHDL tools for sale
********************************************************************
Interpretive Systems
  1270 Oakmead Pkwy
  #209, Sunnyvale, CA 94086
  Tel (408) 749-8775
    Verilog to VHDL compiler
********************************************************************
ITD 
  Institute for Technology Development
  Advanced MicroElectronics Division
  Office Adress:
    1080 River Oaks Drive
    Suite A-250
    Jackson, MS 39208
  contact: Dan Johnson (VHDL modeling group manager)
  phone: (601) 932-7620, fax: (601) 932-7621
  email: danj@aue.com or design@aue.com
  Post Office Box Address:
    Advanced Microelectronics
    P.O. Box 55729
    Jackson, MS  39296-5729
  Corporate Office Phone Number: (601) 960-3600
  Note: Use the corporate office phone to leave messages if the phones have 
      not been connected at River Oaks.
  package of basic gates, conforms to the EIA Commercial Component
  Model Specifications (EIQ-567) and the VHD Data Item Description
  (DIEGDS-80811).  All models include a test bench compliant to the
  Waveform and Vector Exchange Specifications (WAVES PAR 1029.1/D1).
  Back annotation is supported in the timing module.
  SSI model library to be released in July (1991)
  To obtain VHDL SSI model library free, send e-mail to design@aue.com
  with your real mail address; they will send you a license agreement.
  provides contract VHDL modeling services
********************************************************************
Logic Automation
new name: Logic Modelling Corp.
Farley Hall
London Road
Bracknell, Berks RG12 5EU, UNITED KINGDOM
phone: +1 503-690-6900, FAX +44 344 863990
 library of models, 
********************************************************************
LSI Logic Corporation
contact: Doron Mintz, 
email: mintz@lsil.com
phone +1 408 433-8000 in US 800-441-3117,   FAX (408) 433-6802
Silicon 1076:  VHDL development environment, includes the Vantage simulator
and the Synopsys logic synthesizer. Also a high level synthesis module
called Explorer(scheduling binding and allocationfor behavioral code).
links to LSI's MDE environment.
********************************************************************
MCC
3500 West Balcones Center Dr.
Austin, Texas 78759
USA
Phone: +1 (512) 338 3794
 simulator
********************************************************************
Model Technology Incorporated
Contact: Robert Hunter
15455 N.W. Greenbrier Parkway, Suite 240
Beaverton, OR 97006 USA
Phone: +1 (503) 690-6838, FAX: +1 (503) 690-2093,
Email: support@model.com
Australia:       Toby Cross @ GEC Electronics Division     Phone: 02-638-1888
Finland:  Eero Kaikkonen @ Hantro Ky Phone: 358-81-500403
France:  Olivier Thibault @ LEDA S.A.  Phone: 33 76 41 92 43
Germany:         Juergen Weiss @ Spezial Electronic KG     Phone: 5722-2030
Italy:  Eugenio Maragoni @ Instrumatic S.R.L.  Phone: (02) 38103080
Sweden:          Lars-Eric Lundgren @ HARDI Electronics AB Phone: 46-117790
The Netherlands: Chris Van Veenendall @ Translogic BV Phone: 31(0)53-326837
United Kingdom:  Chris Rose @ Saros Technology LTD.        Phone: 0582-410394
Other international: Robert Hunter @ Model Technology - see above
Products: Complete VHDL Compiler/Simulator/Source level debugger
    V-System/PC       Runs on any 640K IBM PC or compatible
    V-System/Windows  Runs on 4Mbyte 286/386/486 systems with Windows 3.0
    V-System/SPARC Requires SunOS 4.1 and Open Windows Version 2.0 or later
    a demo Version for MS-Windows available (full about 6000,- german marks)
All shipping now, supporting full IEEE 1076-1987 VHDL standard (Current PC
    version lacks configuration declarations, Windows & SPARC fully
compliant).
********************************************************************
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777
contact:  Lee Tapper (email: lee_tapper@mentorg.com)
phone: 503-685-7000, FAX 503-685-1268
Germany:
Duesseldorf Sales Office
phone: 0211/591011
Fully integrated compiler/simulator/debugger design development system:
  System-1076 - QuickSim-II based VHDL.  Source-level debugger, supporting
                 VHDL concurrent events.  Integrated in the Concurrent   
                 Design(TM) environment - available now.
  VHDLsim - Explorer Lsim based VHDL.  Focused on IC design, VHDLsim is
             integrated within the GDT design environment, and
             supports the use of VHDL models with analog and M models in 
             the same design.  Available in Q3 1992  
AutoLogic VHDL - VHDL synthesis
VHDLNet - netlist schematics into VHDL structural description
Design Architect - VHDL oriented text editor (and schematic editor)
********************************************************************
Pittsburgh University of [PD/SW?]
Prof. Steven Levitan, 
Dept. of Electrical Engineering
348 Benedum Engineering Hall
Univ. of Pitsburgh, 15261
email: vhdl@ee.pitt.edu
see anonymous ftp: ee.pitt.edu (130.49.15.1) in pub/vhdl-info for files
README, letter.txt, license.PS, assurance.PS ...
not public domain, but 150$ 
 analyzer/simulator and sources 
********************************************************************
Racal-Redac
1000 Wyckoff Ave
Mahwah, NJ 07430
phone (201) 848-2000
FAX: (201) 848-8189
Contact: John Sissler
Germany:
Muthmannstrasse
8000 Muenchen 45
089/32392-0
VHDL 2000 Simulator with GUI, source level debug, supported by Ikos Systems
Accelerator, integrated with Racals Suite of ASIC and System Expert EDA
Tools. Also SilcSyn Synthesis
********************************************************************
Ravi Technologies, Inc.
3080 Olcott St., Suite 220C
Santa Clara, CA 95054
ph: (408) 748-7400  fx: (408) 748-7402
email: savel%ravitech@uunet.uu.net
provides full VHDL services:
 Behavioral models with source code,  Models for synthesis,
 Tutorials for behavioral and synthesis modeling.
 assistance in development and implementation of design methodologies
 suitable to customer needs
********************************************************************
Seeds VHDL ENvironment (SVEN)
 Seed Solutions, Inc.
 7505 Sherman Road
 Chesterland, OH 44026
 216-729-7500
Commercial parser
********************************************************************
Silvar Lisco
703 E. Evelyn Avenue
Sunnyvale, CA 94086
anything in VHDL?
********************************************************************
Swedish Institute of Microelectronics
VHDL CAD tools
Box 1084
S-164 21 Kista -SWEDEN-
contact: Mart Altmae
phone: +46 8-752 1000 FAX: +46 8-750 8056
email: vhdl@inmic.se, ftp: ftp.inmic.se (192.16.125.90)
 MINT		multi-level interactive simulation system
proposed: a Synthesis system
********************************************************************
Synopsys Inc.
USA
Synopsys, Inc.
700 East Middlefield Road
Mountain View, California 94043-4033  U.S.A.
Phone: (415)962-5000
FAX:   (415)965-8637
Germany (moved)
Synopsys, GmbH
Stefan George Ring 2
D-8000 Muenchen 81   Germany
Phone: 89/9939120 
FAX:   89/99391217 
Products:
 Design Compiler - Constraint-Driven Logic Optimization (CMOS & GaAs)
 VHDL Compiler - VHDL Logic Synthesis
 HDL Compiler - Verilog HDL Synthesis
 ECL Compiler - Emitter-Coupled Logic Synthesis and Optimization
 Test Compiler - Test Synthesis (Auto. Test insertion + ATPG)
 VHDL System Simulator - 100% language compatible VHDL behavioral simulation
********************************************************************
The VHDL Consulting Group
974 Marcon Blvd, Suite 260
Allentown, PA 18103
Ph.   : +1 215-882-3130
Fax.  : +1 215-882-3133
Email : vhdl!info@uunet.uu.net
Services : (a) VHDL System Design I seminar (Introduction to VHDL ) 
           (b) Contract VHDL Model Development
           (c) DoD VHDL subcontractor
Products : (a) OEM VHDL Courses for Internal training
           (b) Std_DevelopersKit VHDL Package set (Built upon the IEEE's
		STD_LOGIC_1164 package)
Contact : William D. Billowitch
********************************************************************
University Video Communications
PO Box 5129
Stanford, CA  94309
Phone 415-327-0131, Fax: 408-286-5311
Product: 50-minute videotape; speaker Professor James Armstrong of Virginia
Polytechnic Institute; "Introduction
to VHDL" and discusses uses, characteristics and applications of
VHDL.co-sponsored by the IEEE and ACM; around $60 or less; available in NTSC
and PAL 
********************************************************************
Valid see CADENCE (part of)
********************************************************************
Vantage Analysis Systems, Inc
USA:
42808 Christy Street, Suite 200
Fremont, CA 94538
phone: +1(510) 659-0901 fax: (510) 659-0129
contact: John Willey
Europe:
UK:
Grove Court Business Centre
Hatfield Road
Slough
Berkshire SL1 1QU (UK)
France:
Daniel Langois
MISIL Design
2 Rue De La Couture  Silic 301
94588 Rungis Cedex (France)
Sweden:
Lars Lindqvist :- Engineer
Hardi Electronics
P.O. Box 966
Varvadersvagen 4P
S-220 09 Lund (Sweden)
Phone +46 46 117790
Germany:
Klenzestrasse 11
8045 Ismaning b. Muenchen
089/99652217
Japan:
Okura & Co, Ltd
3-6 Ginza, 2 chome
Chuo-ku, Tokyo 104 (JAPAN)
phone: 011-81-3-566-6000, fax: 011-81-3-563-5447
 Vantage Spreadsheet, 100% IEEE 1076 VHDL Source Code Debugger Concurrent
Compiler  Network License
Integrated VHDL Schematics/Simulator Read/Write Mentor/Valid/EDIF Schematics
Logic Automation & ASIC libraries Hardware Modeller On Sun & HP machines
********************************************************************    
Viewlogic
193 Boston Post Road West
Marlboro, MA 01752
phone: 508/480-0881 or 1-800-422-4660, FAX: 508/480-0882, TELEX 174242
Germany:
R"osrather Str. 544
5000 K"oln 91
phone.: +49-221-861013	FAX: +49-221-866545
Schatzbogen 50
8000 Muenchen 82
089/4201151 
 ViewSim/SD: simulator (behavioual and structural)
 VHDLdesigner: synthesis to gate level
 VIewgen: schematic drawing synthesis (indirectly coupled to EDIF)
 Export.1076: Automatic VHDL model generation from Viewlogic schematic
     (which accepts EDIF)
********************************************************************
Vista Technologies, Inc.
USA:
 1100 Woodfield Road, Suite 108
 Schaumburg, IL 60173-5121
 phone:  (708) 706-9300, fax:    (708) 706-9317
 contact: David Jakopac
 email: dave@vistatech.com
Japan:
 Marubeni Hytech Corp.
 Marubeni Hytech Bldg.
 20-22, Koishikawa 4-Chome
 Bunkyo-ku, Tokyo 112
 JAPAN
 phone:  81-3-3817-4871, fax:    81-3-3817-4880
 contact: Ken Sakamaki
Europe:
 LEDA S.A.
 Europarc, Bat. C
 F-13013 Marseille
 FRANCE
 phone:  33+ 91 06 26 73, fax:  33+ 91 06 24 66
 contact: Olivier Thibault
The VHDL Developer:  VHDL model development environment.  Includes
  Language Assistant for design entry and checking,
  Source Code Library Manager for design reuse,
  over 5000 lines of VHDL examples, and EDIF to VHDL
  translator.
The VHDL Developer Plus:  Same as The VHDL Developer plus Model Creator
  for creating VHDL source from function- and state-
  machine-tables. Can generate code campatible for
  synthesis.
********************************************************************
ZyCad 
  (ZyCads VHDL software was sold to Synopsys)
1380 Willow Road
Menlo Park, CA 94025
  VIP VHDL Instruction Processor
  hardware accelerators
********************************************************************
-- 
dettmer@ls1.informatik.uni-dortmund.de
phone: +49-231 755 6323, FAX: +49-231 755 6555
Thomas Dettmer, Dortmund University, Computer Science I
Post Box 50 05 00, W-4600 Dortmund 50, Germany