🚀 go-pugleaf

The second Ottawa Region VHDL User Group meeting is being held at the

                Lord Elgin Hotel
                Ottawa, Ont.
                Feb 15-16, 1993

The user meeting will include an emphasis on users' experiences with
VHDL, one day modeling techniques and synthesis course, and EDA vendor
presentation & demos.  Here is the agenda for the meeting

  Feb 15th.   Course: VHDL in Modeling and Synthesis
              Cost $100.00 
              A one-day introductory course 
                 By: Prof. E.M Aboulhamid, E. Cerny, U.of.M
     08:30       VHDL Familiarization & Modeling Technique
     15:00       VHDL Modeling for Synthesis.

  Feb 16th.   VHDL User Group Meeting and EDA Presentation
              Cost $15:00 
     09:00       Arrival and Registration
     09:15       DSP Verification and Implementation Using VHDL
                    By: Janick Bergeron, Bell-Northern Research
     10:15       Rapid Development of High-Level VHDL Models
                    By: Karim Khordoc, University of Montreal
     11:15       Case studies of using VHDL for high level design
                    By: Appl. Engineer from Synopsys
     12:00       Lunch
     01:00       Technical Presentations & Demos
                    - VIP Hardware Accelerator by ZYCAD
                    - Demonstration of high level design by Synopsys
                    - Other topics to be announced.

For further information and registration, please contact:

Parviz Yousefpour         Dennis Lenard           Azzedine Boubguira
Bell-Northern Research    Computing Devices Co.   LSI Logic Corp, Canada
P.O. Box 3511, Stat C     P.O Box 8508            Suite 400, 260 Hearst Way
Ottawa, Ontario           Ottawa, Ontario         Kanata, Ontario, K2L 3H1
Tel: (613) 763 8697       Tel: (613) 596 7744     Tel: (613) 592 1263
Fax: (613) 763 7241       Fax: (613) 596 7334     Fax: (613) 592 3253
email: parviz@bnr.ca