Writing a tool to convert digital circuit netlists to VHDL

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1 total messages Started by Daniel R. Kegel Fri, 29 Jan 1993 02:54

#408

Author: Daniel R. Kegel
Date: Fri, 29 Jan 1993 02:54

20 lines
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I'm starting to design a netlist converter in C++ which will 
read in a Futurenet netlist and produce a structural VHDL netlist.
(VHDL is the up-and-coming hardware description language for digital
electronics design & simulation, if you hadn't heard the acronym before.
Futurenet is an el cheapo schematic capture package.)

I want to handle not just simple signals, but also arrays and records
(at least as far as the Futurenet format supports them).
I'm trying to decouple the netlist reading from the netlist writing
by representing the netlist in memory.  This ought to make it easy to 
add new input or output languages, such as EDIF, without having to 
rewrite the whole thing.

Right now, I'm still designing the classes that will make up the
internal representation.  The task reminds me of compiler design at the
moment.

If anyone is interested in working with me on this, or just kibitzing, please 
write me at dank@blacks.jpl.nasa.gov.  
- Dan Kegel

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