🚀 go-pugleaf

  Also, those traveling from out of town will need to make room 
  reservations ASAP to obtain lodging at the Residence Inn. Call 
  1-503-531-3200, and request a room reserved by Cliff Cummings 
  and the Qualis training group rate.  After Monday, June 19th, 
  the reserved-rooms will be released and no longer available.

  Qualis does not anticipate offering another VHDL class until 
  September.

  Regards - Cliff Cummings

  Qualis Training Schedule
  ------------------------
	"A Comprehensive Introduction to Top Down Design Using VHDL"
		Class Dates:	June 26-30
		Time:		8:30 AM to 5:00 PM
		Location:	Residence Inn, Portland West
		                Just West of Beaverton, OR

	"A Comprehensive Introduction to Top Down Design Using Verilog"
		Class Dates:	July 17-21
		Time:		8:30 AM to 5:00 PM
		Location:	Qualis Design Corporation

	Special room rates are available at The Residence Inn for 
	Qualis Training -- contact Qualis for more details.

  Intended Audience
  -----------------
	"A Comprehensive Introduction to Top Down Design Using 
	VHDL (or Verilog)" is intended for hardware and software 
	engineers and system architects who wish to gain a solid 
	grounding in, and wish to understand how to use VHDL or 
	Verilog for system design and simulation.  Others who 
	wish to understand the features and benefits of VHDL and 
	Verilog will also profit from this course.

  "A Comprehensive Introduction to Top Down Design Using VHDL"
  ------------------------------------------------------------
	"A Comprehensive Introduction to Top Down Design Using 
	VHDL" is a fast paced, 5-day hands-on, multi-media course 
	designed not only to teach the entire VHDL language, but 
	to make class participants immediately productive in a 
	synthesis and system simulation environment using 
	state-of-the-art tools.
	
	Students will have access to individual Sun Sparcstations, 
	the Synopsys VSS simulation environment, and the Synopsys 
	DC Expert synthesis environment for use during the 
	laboratory sessions.  After an introduction to VHDL, the 
	course deviates from the bottom-up, gates-to-behavioral 
	modeling presentation of traditional course materials and 
	reverses the flow, teaching top-down design practices, 
	with early special emphasis on coding for synthesis, 
	efficient testbench generation and advanced design 
	verification techniques. These skills are reinforced 
	throughout the week while teaching VHDL from a top-down 
	perspective.

  About the Instructor
  --------------------
	"A Comprehensive Introduction to Top Down Design Using 
	VHDL" is taught by Janick Bergeron, Qualis Director of 
	Technology and Principal Engineer, who has completed many 
	ASIC designs and system simulation projects.
	
	Mr. Bergeron is capable of answering the very technical 
	questions asked by experienced design engineers.
	
	Mr. Bergeron has presented dozens of introductory, 
	intermediate and advanced workshops and tutorials on 
	topics including top-down design, test methodology, 
	bus-functional modeling, logic synthesis, generation of 
	EDIF from VHDL and introduction to modeling using both 
	VHDL and Verilog.  One of Mr. Bergeron's works was voted 
	Best Paper at the 1991 European VHDL Users Forum. He was 
	also a member of the technical program committee for the
	1995 Spring VHDL International Users Forum.

	Mr. Bergeron holds a B.Eng from the Universite du Quebec 
	a Chicoutimi and an M.A.Sc. in EE from the University of 
	Waterloo.  Mr. Bergeron is an active member of the IEEE.
	
  Additional Information
  ----------------------
	Course fee includes all training materials and books, daily
	continental breakfast, full lunch, afternoon refreshments,
	framed course completion certificates and awards.

	For more information about Qualis Top-Down courses, including 
	course description and syllabus, contact us at:

                            Qualis Design Corporation
                           15455 NW Greenbrier Parkway
                                   Suite 250
                              Beaverton, OR  97006

                             Phone: (503) 531-0377
                            E-mail: training@qualis.com
			   (please specify which course)

  E-Mail Updates
  --------------
        Information about advanced Top-Down training using Verilog 
        & VHDL is e-mailed to engineers who may be interested in 
        current and future Qualis training and seminars including: 
        Testbenches & Synthesis using Verilog or VHDL, Synthesis 
        for FPGAs, Advanced HDL project strategies, LM Hardware 
        Modeling for Verilog or VHDL, Co-simulation using Verilog 
        & VHDL.  
	
        If you would like to be added to our e-mail distribution 
        list, please send your name and e-mail address to 
	training@qualis.com 
	
        Qualis also publishes Verilog, VHDL, and 1164-Package 
        Quick Reference Cards which will soon be available at a 
        Qualis FTP site where engineers will be encouraged to 
        freely copy postscript versions of these Cards for 
        personal and company use. Details will be e-mailed at a 
	later date.

  About Qualis Design Corporation
  -------------------------------
	Qualis Design Corporation is the leading independent 
	provider of top-down consulting, design, and training 
	services.  The company provides services to leading-edge 
	high technology firms worldwide.  Qualis HDL Training 
	Courses are conducted on leading-edge Sun workstations 
	using the latest EDA vendor tools, and are taught by 
	engineering professionals with extensive digital design 
	experience.  Engineers who complete the Qualis VHDL & 
	Verilog Training Courses will be more efficient users of 
	system simulation tools, will be capable of implementing 
	advanced simulation environments, and will have the 
	knowledge to successfully complete complex design 
	projects.  Engineers with previous exposure to VHDL and 
	Verilog will also benefit from the leading-edge material 
	presented.

  ----------------------------------------------------------------------------
  Copyright (c) 1995 Qualis Design Corporation.  All rights reserved.

  "DC Expert" is a trademark of Synopsys, Incorporated
  "Verilog" is a registered trademark of Cadence Design Systems


  Regards - Cliff Cummings

============================================================================
=  Cliff Cummings - Director of Training, Principal Engineer
=                   Verilog/Xilinx/LMC Training, Consulting & Contracting
=  Qualis Design Corporation
=  Suite 250                              E-mail: cliffc@qualis.com
=  15455 N.W. Greenbrier Parkway          Voice:  (503) 531-0377
=  BEAVERTON OR 97006                     FAX:    (503) 629-5525
============================================================================