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Started by Simon Curry
Wed, 31 Mar 1993 03:33
VHDL International Users Forum '93
Author: Simon Curry
Date: Wed, 31 Mar 1993 03:33
Date: Wed, 31 Mar 1993 03:33
470 lines
18802 bytes
18802 bytes
VHDL International Users' Forum
Spring 1993 Conference
Sponsored by VHDL International
"Making VHDL a Commercial Reality"
==================================
April 28 - 30, 1993
Chateau Laurier Hotel
Ottawa, Canada
To be held immediately following the
IFIP Conference on Hardware Description Languages (CHDL)
The Conference
--------------
VHDL has emerged as the standard for performing high-level design
and the recently-adopted changes in the language specification have
helped fill the gaps in the original standard. Now, as more and
more designers are becoming proficient at using an HDL-based design
methodology and as EDA vendors' tools continue to mature, its
popularity has grown beyond its roots as a DoD-mandated format.
This edition of the bi-annual VIUF will focus on the commercial
implementation of a VHDL-based design methodology. Participants
will explore the issues, obstacles and benefits in using VHDL to
design custom ICs, ASICs and systems in the context of the
high-pressure electronics products industry.
The conference will include an emphasis on users' experiences with
VHDL for a broad range of applications.
[ This file is intended as a guide, only. Should circumstances
warrant, the program may be changed without notice. There
follows the conference program, a tutorials' description,
general registration information and an enrollment form.]
Technical Program
-----------------
WEDNESDAY - APRIL 28TH
======================
10:00 - 4:00 Registration
------------
1:30 - 3:30 Welcome
-------
Victor Berman - Conference Chair
Simon Curry - Program Chair
Announcements
-------------
Michael Carroll - President VHDL International
VHDL '92 Update
---------------
Victor Berman
Cadence Design Systems, Inc.
3:30-4:00 Refreshment Break
-----------------
4:00 - 5:30 Session I - VIUF/CHDL JOINT PANEL ON STANDARDS
----------------------------------------------
4:00 - 8:00 Exhibits Open
-------------
6:00 - 8:00 Welcome Reception (in Exhibit Hall)
-----------------------------------
THURSDAY - APRIL 29th
=====================
7:30 - 3:00 Registration
------------
8:30 - 10:00 Session II - SYNTHESIS
----------------------
Chair: Cary Ussery - Cadence Design Systems, Inc.
A Multicomponent Synthesis Environment for VHDL Specifications
R.Vemuri, N.Kumar, N.Ren, Ram Vemuri - Univ. of Cincinnati
Partitioning for Multicomponent Synthesis from VHDL Specifications
N. Kumar, Ram Vemuri, R. Vemuri- Univ. of Cincinnati
Synthesis of Testable Control Hardware
P. M. Campbell - Northeastern University
Z. Navabi - Univ. of Tehran
Module Generation for VHDL Synthesis
R. Dekker, M. Ligthart - Exemplar Logic
10:00 -10:30 Refreshment Break
-----------------
10:30 -12:00 Session III - USERS' EXPERIENCE
-------------------------------
Chair: Parviz Yousefpour - Bell Northern Research
Experiences in Real-Time Hardware-Software Co-Simulation
W.M. Loucks, B.J. Doray, D.G. Agnew - Bell-Northern Research Ltd.
Interactive Models and Testbenches in VHDL
H. Thaker, J. Bergeron - Bell-Northern Research Ltd.
VHDL and its Application for Department of Defense Contracts
A. E. Rosenberg - Zycad Corporation
T. Harris - Wright-Patterson AFB
Modeling for Fault Insertion and Parallel Fault Simulation
Z. Navabi, R. Liyanage - Univ. of Tehran
N. Cooray - Northeastern University
12:00 - 1:30 Lunch
-----
1:30 - 3:00 Session IV - MODELING METHODOLOGY
---------------------------------
Chair: Gabe Moretti - Intergraph Electronics
A Universal Structural VHDL Library for ASIC Simulations
J. Caisso, J. Halle - MATRA-MHS
Modeling Techniques Using VHDL/C-Language Interfacing
B. K. Fross - Supercomputing Research Center
V-Charts: A Visual Formalism for VHDL
D. R. Smith, D. E. W. Mercer
Royal Military College of Canada
Petri Net Based Analysis of VHDL Behavioral Models
N. Stollon - Texas Instruments
3:00 - 3:30 Refreshment Break
-----------------
3:30 - 5:00 Session V - SIMULATOR PERFORMANCE
---------------------------------
Chair: Dinesh Bettadapur - Intel Corporation
Gate-level Simulation in VHDL
J. Sissler, B. Fazakerly, N. Qureshy - Ikos Systems
High-Level VHDL Simulator Running on Logic Simulation Machines
M. Shoji, F. Hirose - Fujitsu Laboratories Ltd.
Performance: The Native Code Approach
V. Berman, C. Ussery, G. Ordy, P. Hubbard - Cadence Design Systems
A Behavioral VHDL BUS Functional Model for the Pentium (TM)
Processor
S. Hunt, A. Mehta, D. Patterson, S. Shah - Intel
3:30-7:30 Exhibits Open
-------------
FRIDAY - APRIL 30th
===================
7:30 - 10:00 Registration
------------
8:30 - 10:00 Session VI - PERFORMANCE AND SYSTEM MODELING
--------------------------------------------
Chair: Steve Bailey - Vantage
VHDL-based Methodology for Modeling Performance of Parallel
Systems
P. Chawla, H. Hirsch - MTL Systems, Inc.
Modeling of a Futurebus + System Architecture Using VHDL
R. Schetlick - Zycad Corporation
System-Level Modeling of Equalizers Using VHDL
R. de Fermin, D. Perez, F. Reguero - Alcatel SESA RSD
Self Adjusting Unidirectional Switch Models for Dynamic Load
Calculation and Fast Switch Level Simulation
Z. Navabi, Z. Razavi - University of Tehran
10:00 -10:30 Refreshment Break
-----------------
10:30 - 12:00 Session VII - PERFORMANCE AND SYSTEM MODELING
---------------------------------------------
Chair: Tedd Corman - Viewlogic
Configurable VHDL Models for Field Programmable Gate Arrays
M. R. Movahhodin, Z. Navabi - University of Tehran
Using Top-Down System Simulation (TDSS) to Develop a Wireless LAN
System
C. M. Costa - Zycad Corporation
Modeling Techniques with VHDL for Jitter Performance Analysis
M. Bourahla, K. Soh, E. Aboulhamid, S. Curry - Bell Northern
Research
Topdown ASIC Design Using VHDL
Z. Khan - Intel Corporation
12:00 -1 :30 Lunch
-----
1:30 - 3:00 Session VIII - DESIGN METHODOLOGY
---------------------------------
Chair: J. Scott Calhoun - Mississippi State University
VHDL Design Methodologies and Management
J. S. Hong, J. Lutz - LSI Logic Corporation
Testview: An Innovative Approach To Automatic VHDL Testbench
Generation
S. Smith - Mississippi State University
Specification of Interface Behavior for the Automatic Generation
of Bus-Interface Models
A. J. Daga, W. P. Birmingham - University of Michigan
An Object-Oriented Schema for Electronic CAD Tools
E. Hughes, L. Huang, E. J. Golin - Univ. of Illinois at
Urbana-Champaign
3:00 - 3:30 Refreshment Break
3:30 - 5:00 Session IX - CAD TOOL ENVIRONMENT
Chair: Paul Menchini - Menchini Consultancy
Parallel Simulation: Self-Extraction of the Natural Parallelism of
VHDL Models
Y. Herve - ENSPS/LSIT
Generic Design: Its Importance, Implementation and Limitations
K. ten Hagen, H. Meyr - Aachen University of Technology
Developing a VHDL Timing Package for Calculating Delays/Timing
Constraints
B. Tsai - Integraph Electronics
Automatic Generation of Timing Annotated VHDL Models of VLSI
Circuits
R. Krishnamurthy, J. DeGroat - Ohio State University
BIRDS OF A FEATHER
Birds of a Feather sessions will be held on Thursday at 8:00 pm. Be
sure to sign up your topics for discussion at Registration!
----------------------------------------------------------------------
TUTORIALS
Wednesday, April 28, 1993
7:00 - 9:00 am Tutorial Registration
8:00 am - 12:00n Tutorial A
EXPERIMENTING WITH VHDL
Joseph Pick - CLSI Solutions
This tutorial will present and analyze a set of experiments that
both challenge and reinforce the participant's understanding of how
the various VHDL constructs behave and interact with each other.
Potential problems are illustrated via an experiment and then
creative solutions to these difficulties are demonstrated.
Participants gain a better understanding and appreciation of VHDL
by observing the language in action. Learn problem solving skills
at all levels of VHDL expertise.
8:00 am - 12:00n Tutorial B
DESIGNING WITH VHDL
Bill Fazakerly - Ikos Systems
A system with 250,000 gates in ASIC/FPGA along with hundreds of
megabytes of RAM has been designed in VHDL. Design capture,
simulation, and synthesis tools from a variety of vendors were used
on the project. The system simulations included 400,000 gates,
simulated at the gate level, along with a host of VHDL models and
a VHDL test bench. This tutorial will disclose how the project was
organized and how VHDL was used. We will discuss the problems that
were encountered and how they were solved.
8:00 am - 12:00n Tutorial C
LEARNING TO USE WAVES BY EXAMPLE
Richard Unkle - IIT Research Institute
This tutorial will take a bottom-up approach to creating a WAVES
dataset using a simple device as an example. The example will be
used throughout to introduce basic WAVES concepts and to explain
the minimum requirements for a WAVES dataset. A more complex
example will also be introduced along with the means to use WAVES
in a VHDL environment. Also, a WAVES/VHDL interface package will be
presented. The goal of the tutorial is to provide the required
knowledge of how to use WAVES.
8:00 am - 12:00n Tutorial D
AN INTRODUCTION TO VHDL
AND THE '92 UPDATES TO THE STANDARD
Krishna Kumar - Cadence Design Systems, Inc.
This tutorial is designed to teach the various aspects of VHDL to
a beginner and will also cover the '92 updates. Emphasis will be
placed on the usage of VHDL and the various styles of descriptions.
The tutorial will expose the participant to the power, flexibility,
and the generality of VHDL. Language concepts will be taught, using
relationship to existing hardware (wherever possible). This
tutorial will be a good starting point for engineers and managers
who are new to the language.
----------------------------------------------------------------------
GENERAL INFORMATION
LOCATION / HOTEL
All general sessions, tutorials and exhibits will take place at the
Chateau Laurier Hotel in Ottawa, Canada. The Chateau Laurier is located
in the heart of the city at 1 Rideau Street in Ottawa, Ontario, Canada
KlN 8S7. The hotel is located 12 miles (20 minutes) from Ottawa
International Airport.
The hotel is offering a special VIUF Conference rate of $118 (Canadian)
for a single or double room. Rates are good while rooms are available
and if booked by March 27th. Call the Chateau Laurier at 1-800-828-7447
(USA) or 1-800268-9411 (Canada) for your reservation. For travelers
outside the U.S. and Canada, you may call the hotel direct at
613-232-6411. Be sure to ask for the special VHDL International Users'
Forum (VIUF) Conference rate.
TRANSPORTATION - PARKING
Transportation from Ottawa International Airport to the hotel is
available via Pars Transportation Service. Pars buses operate seven
days a week, with service every half hour from 5:40 am to 1:10 am. You
can catch the Pars bus outside of the Arrivals section of the airport.
The cost for service to the Chateau Laurier is $8.50 for one-way and
$14.00 for roundtrip. Call Pars at 613/523-8880 for more information.
Cab fare from the airport to the hotel is approximately $20.00 U.S.
Parking is available at the Chateau Laurier at a cost of $12.00 per
day.
AIRLINES - Air Canada & United Airlines
Air Canada and United Airlines are offering joint fares to VIUF
attendees with up to 50% savings on travel between the U.S. and
Canada on regular Hospitality Class fares (pending availability) and a
minimum of 15% savings on the full Hospitality and Executive Class
Services. To make reservations and receive these discounts, call
1-800-3617585 in the U.S. and Canada. Be sure to instruct your ticket
agent to enter our Event Number CV930888 in the tour code box and
Reference Code CMS-4 in the Endorsement Box, regardless of the fare
purchased.
International delegates should contact the following Air Canada
offices: Frankfurt - 25 01 31; Geneva - 731-4980; London - (081)
7592636; Paris - (1) 43201200; Vienna - (0222) 5861909; and Zurich -
2110777.
SPECIAL SERVICES
For information or assistance with disabled or other special services,
please contact Conference Management Services at 415-329-0510 or
415-324-3150 (FAX).
----------------------------------------------------------------------
ADVANCE REGISTRATION
Please complete the attached registration form and return it with full
payment postmarked by April 14th, 1993. Registrations received after
April 14th and at the Conference will be on a space-available basis and
will not be eligible for the Advance Registration discount. Conference
Registration includes admission to all General Sessions, Exhibits and
one copy of the Conference Proceedings. Each Tutorial Registration
includes admission to one tutorial and a copy of that tutorial's
session materials.
FEES: By 4/14 At Conference
Conference Registration $240 $290
VI Technical Member Fee* $200 $250
Tutorial A, B, C, or D $125 $175
* VI Individual Technical Members receive a $40.00 discount off the
Conference Registration Fee only.
Student Registrations: Full time students at an accredited institution
are eligible for a discounted Student Conference and/or Tutorial
Registration fee of $60 (each). Student registrations are accepted
on-site on an as-available basis only.
Payment - Advance registration may be paid by check (in US funds
payable on a US bank), or by VISA or Mastercard. All credit card
registration must include the full credit card number, your name as it
appears on the card, and the card expiration date. Make checks payable
to: VIUF Spring 1993 Conference.
ON-SITE REGISTRATION HOURS
Wednesday - April 28 7:00 am to 4:00 pm
Thursday - April 29 7:30 am to 3:00 pm
Friday - April 30 7:30 am to 10:00 am
BE SURE TO REGISTER BY APRIL 14TH TO RETRIEVE
THE EARLY REGISTRATION DISCOUNT!
----------------------------------------------------------------------
VIUF Spring 1993 Conference * April 28th 1993
Name _______________________________________________________________
Affiliation ________________________________________________________
Address ____________________________________________________________
__________________________________________ Mail Stop _______________
City _______________________ State _____________ Zip ______________
Phone ______________________________________________________________
REGISTRATION FEES: by 4/14 On-Site Due
Conference: $240 $290 ________
VI Technical Member: $200 $250 ________
Member #: ____________________________
Tutorial A: $125 $175 ________
Tutorial B: $125 $175 ________
Tutorial C: $125 $175 ________
Tutorial D: $125 $175 ________
TOTAL: ________
CREDIT CARD PAYMENT:
Name (as it appears on your credit card)
____________________________________________________________________
Credit Card Number:
____________________________________________________________________
Exp. Date: _________________________________________________________
I agree to pay the above total amount according to the card issuer
agreement.
Signature: _________________________________________________________
Please complete this form
and mail or fax it to:
VIUF Spring 1993
407 Chester Street
Menlo Park, CA 94025
Phone: 415-329-0510 � FAX: 415-324-3150
--
---------------------------------------------------------------------
Simon Curry Tele: (613)991-9001
The Royal Society of Canada Fax: (613)991-6996
PO Box 9734, Ottawa K1G 5J4 Email: curry@doe.carleton.ca
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