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Article #609Re: router effeciency
From: Stephen Sugiyama
Date: Mon, 22 Apr 1991 16:37
Date: Mon, 22 Apr 1991 16:37
45 lines
2675 bytes
2675 bytes
In article <11963@exodus.Eng.Sun.COM> (Renu Raman) writes:
> We have some outside routers and some inhouse routers and am trying to
> compare the relative effeciency of these routers. One layman metric is
> router efficiency which has been defined in atleast 2 different ways. I
> would like to know what is the common understand of it
>
> (This is mostly related to chip routers - specifically block routers)
>
> a) router efficiency: Ratio of routed area to total core area (where
> total core area is die size minus pad rings)
> b) router efficiency: Ratio of routed area to total block areas
> where block areas is sum of areas of the blocks in the core (not pad)
>
> GIven (a) or (b) - first tell me which one is the correct one and then
> would like to know - what are the numbers for custom chips (probably manual)
> semi-custom chips (using automatic block routers) for dice in the 12-15mm
> range?
Well, I think router efficiency numbers are almost always suspect, and
here are a couple of reasons why:
1. The efficiency (at least as you've defined it) is design
dependent. A design with two large blocks and two nets is going to
have an efficiency approaching one. A design with two small blocks
and, say, 500 nets will have an efficiency approaching zero.
2. Routers are very placement dependent. Different placements will
cause the same router to produce different results for the same
design. One router may perform better than another router on one
placement, but on a different placement the reverse will be true.
You can't separate routing from placement.
> Renukanthan Raman ARPA:ram@sun.com
> M/S 16-11, 2500 Garcia Avenue, TEL :415-336-1813
> Sun Microsystems, Mt. View, CA 94043
There are many other reasons why it is difficult to evaluate routers,
but I won't go into them here. Are you familiar with the MCNC layout
benchmarks? Krzysztof Kozminski will be discussing their status in a
paper at the 1991 Design Automation Conference.
I hope that this is somewhat helpful.
--
Stephen Sugiyama
ole!sss@sumax.seattleu.edu
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!lll-winken!elroy.jpl.nasa.gov!usc!rpi!batcomputer!cornell!uw-beaver!milton!sumax!polari!thebes!ole!sss From: sss@ole.UUCP (Stephen Sugiyama) Newsgroups: comp.lsi.cad Subject: Re: router effeciency Message-ID: <1908@ole.UUCP> Date: 22 Apr 91 16:37:56 GMT References: <11963@exodus.Eng.Sun.COM> Reply-To: ole!sss@sumax.seattleu.edu (Stephen Sugiyama) Organization: Seattle Silicon Corporation, Bellevue, WA. Lines: 45