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Article #644Re: Why no tri-state outputs in FPGA cells?
From: Steve Golson
Date: Thu, 24 Dec 1992 01:38
Date: Thu, 24 Dec 1992 01:38
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In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes: >Hello, > >I've been working on a project designing a processor with FPGA's. One severe >limitation I found is that their cells do not have tri-state outputs and thus >forcing me to use MUXes on buses consuming a lot of the resources. > >Does anybody have any idea why they didn't make these cell outputs tri-state? Possibly for the same reason that gate array vendors often don't allow tri-state buses inside a design: it's hard to guarantee that you always have only one driver on the bus (i.e. no multiple drivers, and no floating buses). -seg Steve Golson -- Trilobyte Systems -- Carlisle MA -- sgolson@trilobyte.com "As the people here grow colder, I turn to my computer..." -- Kate Bush
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Newsgroups: comp.lsi.cad,comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!psinntp!trilo!sgolson From: sgolson@trilobyte.com (Steve Golson) Subject: Re: Why no tri-state outputs in FPGA cells? Message-ID: <1992Dec24.013854.11226@trilobyte.com> Organization: Trilobyte Systems References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> Date: Thu, 24 Dec 1992 01:38:54 GMT Lines: 18