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In article <1992Nov11.175742.12884@risky.ecs.umass.edu>, obiliset@duke.ecs.umass.edu (Sashi V Obilisetty) writes:
> I guess the best way to ensure that there is no skew is to have
> one big buffer, and then have lines from this driver feeding all
> other modules requiring clocks. What I am concerned about is the
> amount of heat/power dissipation that would occur due to this big
> driver.
> Won't it create a hot spot on the chip? The power supply is 3.3V, 
> is this the reason why it works?

  When looking at the micro photograph taken from the Alpha
  (SC-27, nov. 1992, p.1556), it is clear that the buffer is
  not just a small sub-circuit, it takes about 10% of the
  total active area of the chip. So the clock generator wouldn't
  cause a hot _spot_, but a less hot _region_. 

> 
> Also, the chip is designed using 0.75um process with min. channel
> lengths of 0.5um. How can we have long lines running in this technology?
> Wouldn't the transmission line effects become prominent at this point,
> and therefore it makes sense to use distributed driving??

  The transmission line effect is most of significance when dealing
  with high-resistive wires, like poly-silicide.  However, the 
  Alpha people used metal for interconnection, quote:

   "Metal 3 is very thick and has relatively large pitch. It is
    important at these speeds to have a low-resistance metal
    layer available for power and clock distribution."

  Some figures. I'm using an 1.6u CMOS technology, with
  the following sheet resistance for the various layers (typical):

  metal 1      : 45 milli_ohm/square
  metal 2      : 30 milli_ohm/square
  poly silicon : 25 ohm/square 

> 
> Will be glad if someone would clear these doubts.
> Thank You.
> 
> Sashi

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  Rene Bodenstaff
  Delft University of Technology
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