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Article #677Re: Why no tri-state outputs in FPGA cells?
From: Jeff Jensen
Date: Tue, 15 Dec 1992 16:55
Date: Tue, 15 Dec 1992 16:55
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One possible reason is that the implementation of tri-statable outputs usually includes an additional series pass transistor in the output path of the cell. This additional resistance causes additional delay. Given that speed limitations are a critical problem for FPGAs, you don't want to build in a fixed additional delay. Jeff Jensen Neocad -- Jeff Jensen Neocad Inc. 2585 Central Ave. Boulder, CO 80301 (303) 442-9121 X116 Internet: jensen@neocad.com UUCP: neocad!jensen ---------------------------------------------------------------------- "... watch from high atop Tokyo Tower as the twisted world you created
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arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!magnus.acs.ohio-state.edu!csn!neocad!jensenShow Full Headers
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Newsgroups: comp.lsi.cad Path: arc1-ca.pugleaf.net!sparky!uunet!zaphod.mps.ohio-state.edu!magnus.acs.ohio-state.edu!csn!neocad!jensen From: jensen@neocad.com (Jeff Jensen) Subject: Re: Why no tri-state outputs in FPGA cells? Message-ID: <1992Dec15.165528.991@neocad.com> Organization: NeoCAD, Inc. Date: Tue, 15 Dec 1992 16:55:28 GMT Lines: 14