🚀 go-pugleaf

In article <1992Dec15.010020.9274@super.org> cfreese@super.org (Craig F. Reese) writes:
>
>You don't say which FPGA you are using but the Xilinx 4000 series does
>contain tristate buffers for just the kind of purpose you describe.
>The buffers are not on each CLB but adjacent.  There are some
>limitations as to where the buffers can connect up.  I have found
>designs where the functionallity did _not_ work for a given device (due
>to the size of the FPGA, size of my design, and the tristate buffer/bus
>resources) but a larger chip probably would have.  In many other
>designs I have not used any tristate logic (so I'm glad the CLBs aren't
>all tristate by default).


I am working with Pichet (the originator of this thread) on a very 
similar design, and I think his question can be rephrased.  What we
are really trying to figure out is 

Is there an electrical reason why the short pieces of interconnect 
(those that are connected through Xilinx's 'PIP's) cannot be tristated?

The long lines obviuosly don't present any electrical problems as they 
are simply edge to edge pieces of wire.  Are the pass transistors in 
the interconnect points the problem? 

Here's the motivation for our inquiries...

With the current Xilinx parts (I am using XC4010's) the number of
busses that can be implemented is severely limited by the number
of long lines.  In a design that requires many wide busses (I am
currently working on a 32 bit microprocessor) the number of long
lines available is not enough to implement a true bus structure.
As a result, I am forced to use a large number of fairly wide
multiplexers, and a correspondingly large number of CLBs and routing 
resources.  The ability to tristate the output of each CLB while
attaching it to a piece of "normal" routing would eliminate (or
reduce) bus constraints on chip, in addition to (possibly) freeing 
up some of the CLBs that were previously used for bus redirection
to be used for "useful" logic.

Thanks for any insights,
Tad Truex