🚀 go-pugleaf

I don't know of a software tool that can handle your Pin Assignment
problem, but I'll comment on your overall plan.

You're over simplifying by assumming an "in-house design" provides
"full control over the process" (of assigning pin locations) since
who manufactures the ICs and who within your company approves spending
(money) are going to limit `your control'.  For example:

1]  All Gate-Array ASIC suppliers have a limited number of package
    options available and many packages have limitations on power
    and ground locations.  This is very true of high pin count
    ceramic packages.

2]  If you're generating the packaged units in-house then your purchasing
    folks will want `open-tooled' packages selected instead of custom
    designs that can cost $45K+ to design and tool.

3]  Even if all the ICs are in PQFPs with no PQFP Vendor restrictions
    on pin assignments you'll still have pin placement restrictions due
    to the actual IC functions.

    IC -a- could be designed on a FAB process and set of design rules that
    requires one power/ground pair per every eight output pads while IC
   -b- needs one pair per four outputs.  If both devices have the same
    footprint and drive the same bus you're going to be hard pressed to
    find a single solution.

These are real world issues and very dependant on the IC functions,
design rules, and process performance while they have less to do with
`in-house design and control' of the ICs themselves.  ASIC package selection
is still treated as a low-tech no brainer that causes endless confusion
for IC designers and ASIC suppliers (like me) late in a design cycle.

Good Luck.
            Craig Bender
            Product Engineer
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