Prolog Algorithm

Article View: comp.lsi.cad

Article #890

#890

From: Mehmet Yavuzer
Date: Wed, 03 May 1989 18:11

9 lines
765 bytes



I  am looking for a good Prolog algorithm for placement of
logic gates in vertical order where the objective is to
minimize number of wire intersections between adjacent levels
of gates.
This algorithm is intended to be used with a schematic layout
generator for networks of logic gates.

Technical Details

Message-ID: <1497@cmx.npac.syr.edu>

Path:

arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!husc6!psuvax1!psuvm.bitnet!cunyvm!!cmx!sutcase.case.syr.edu!myavuzer

Show Full Headers

Complete Article Headers

Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!husc6!psuvax1!psuvm.bitnet!cunyvm!!cmx!sutcase.case.syr.edu!myavuzer
From: myavuzer@sutcase.case.syr.edu ( Mehmet Yavuzer)
Newsgroups: comp.lsi.cad
Subject: Prolog Algorithm
Message-ID: <1497@cmx.npac.syr.edu>
Date: 3 May 89 18:11:09 GMT
Sender: usenet@cmx.npac.syr.edu
Reply-To: myavuzer@sutcase.case.syr.edu ( Mehmet Yavuzer)
Distribution: usa
Organization: CASE Center, Syracuse University
Lines: 9