ECAD Software

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Article #948

#948

From: Colley M J
Date: Wed, 06 Apr 1994 11:42

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Now available via anonymous FTP from: ftp.essex.ac.uk

A Xilinx xnf -> verilog translator for generating postlayout verilog models
of placed and routed designs (XC3000 series only).

A Cadence Edge design kit for Xilinx XC3000 series devices. Allows schematic capture,
simulation, netlisting and postlayout simulation. Place and route must be done via
Xilinx tools.

These tools can be found in /pub/csc/ecad in source form.

Martin Colley

martin@essex.ac.uk

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From: martin@essex.ac.uk (Colley M J)
Newsgroups: comp.lsi.cad,eunet.esprit.eurochip,comp.lang.verilog
Subject: ECAD Software
Keywords: Cadence Edge, Verilog, Xilinx, FPGA
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Date: 6 Apr 94 11:42:57 GMT
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Organization: Department of Computer Science, University of Essex, England
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