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Started by Joan Pache
Tue, 25 Jan 1994 21:31
Deadline now March 1st, 1994
Author: Joan Pache
Date: Tue, 25 Jan 1994 21:31
Date: Tue, 25 Jan 1994 21:31
360 lines
14596 bytes
14596 bytes
> Registration Deadline now MARCH 1st, 1994 <
-----------------------------------------
BiCMOS TECHNOLOGY, MODELING, ANALOG and DIGITAL
DESIGN and APPLICATIONS
April 18th - 20th, 1994
Valhalla Inn
Kitchener, Ontario, Canada
Sponsored by:
VLSI Research Group
University of Waterloo
Institute for Computer Research
University of Waterloo
Information Technology Research Centre
KW Section of the IEEE
Organizer:
Professor M.I. Elmasry,
University of Waterloo
Waterloo, Ontario, Canada
THE COURSE:
BiCMOS has changed the way circuit design has been done for gen-
erations. For the first time, both bipolar and MOS devices are
available on the same chip, offering a unique, but challenging
opportunity to VLSI designers to use such devices to meet the
ever increasing demands on VLSI systems.
This course is designed to cover the basic as well as the state-
of-the-art design issues related to BiCMOS design. A general
knowledge in device physics, processing and circuit design is
assumed. BiCMOS processing technology, device and circuit model-
ing, analog and digital circuit design and their applications
will be covered. Seven top experts on BiCMOS design, both from
university and industry, are the instructors of this course
offering 21 hours of intensive course material.
ACADEMIC CREDIT:
No academic credit is offered for this course, although a Certi-
ficate of Completion will be issued to the course participants.
WHO SHOULD ATTEND:
Engineers, scientists, engineering managers and graduate students
involved in integrated circuit design. Processing and modeling
specialists will also find the course useful.
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REGISTRATION INFORMATION:
Registration Fees : $1,350.00 Cdn. (GST included)
Members of ITRC, ICR, IEEE and universities are eligible for 15%
discount. The registration fee includes copies of course
material, lunch and refreshments. Early registration is
encouraged as the course participants are limited. REGISTRATION
DEADLINE IS MARCH 1, 1994. A late registration fee of $100.00
Cdn. will be charged after MARCH 1, 1994.
CANCELLATION/REFUND:
A cancellation fee of 20% is applicable if cancellation is made
up to March 18, 1994. After that date no refunds will be
allowed.
LOCATION and ACCOMMODATION:
All course activities and accommodation will be at the Valhalla
Inn, 105 King Street East, Kitchener, Ontario N2G 2K8; Toll free
in Canada and USA 1-800-268-2500, Telephone (519)744-4141; Fax
(519)578-6889. A block of rooms is reserved for the course par-
ticipants. Please make accommodation arrangements directly with
the hotel. Room rates are $75.00 single and $85.00 double.
Please identify yourself as a "Waterloo Course Participant" when
you make your booking.
A brochure of the Valhalla Inn containing a map of the local area
is available on request.
The Kitchener-Waterloo area is approximately 1 hour drive
south/west of Toronto's International Airport; 1 1/2 hour drive
from Buffalo and a 3 hour drive from Detroit. Door-to-door
ground transportation is available from Toronto International
Airport to the Valhalla Inn by calling Airways Transit (519)886-
2121.
While you are in the Kitchener-Waterloo area experience its
unique German heritage by visiting our farmer's markets or coun-
try inns for a "stick-to-your-ribs" meal in Mennonite country.
Or take a quiet drive in some of Ontario's most picturesque coun-
tryside. Come, be captivated by the warmth...the old fashioned
charm of the Kitchener-Waterloo Area.
FOR FURTHER INFORMATION and REGISTRATION:
Mrs. Joan Pache
VLSI Research Group
University of Waterloo
Waterloo, Ontario, N2L 3G1 Canada
Telephone (519)888-4084 Fax (519)746-5195
jpache@vlsi.uwaterloo.ca
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PROGRAM
------------------------
Monday, April 18th, 1994
---------------
Morning Session: 9:00 a.m. - 12:30 p.m.
Paul Kempf, Northern Telecom Limited
BiCMOS Processing Technology
Historical Perspective, Device Technology, Device Design and
Optimization, CMOS/Bipolar Tradeoffs, Process Flow, Device Scal-
ing, Isolation and Interconnect.
---------------
Afternoon Session: 1:30 p.m. - 5:00 p.m.
Jim Kendall, Northern Telecom Limited
BiCMOS Circuit Modeling
Design and Simulation Issues; Modeling the Bipolar and MOS
Transistors - SPICE Models and Alternatives; High Speed Modeling;
Parameter Extraction; Parameter Scalability and Margining; and
Capacitance, Resistance and Parasitics.
---------------
Evening Session: 5:30 p.m. - 7:00 p.m.
A. Bellaouar, University of Waterloo
BiCMOS Design : Tutorial I
Example of BiCMOS Circuit Families, Effect of Device Parameters
on Circuit Performance, Simple Circuit Blocks, Circuit Simulation
and Performance Evaluation.
-------------------------
Tuesday, April 19th, 1994
---------------
Morning Session: 9:00 a.m. - 12:30 p.m.
M.I. Elmasry, University of Waterloo
BiCMOS Digital Design
Basic Digital Blocks, Circuit Optimization, Low-Voltage Low-Power
Operation, High-Performance BiCMOS, the Role of ECL, Level-
Translators, BiCMOS vs. CMOS, BiNMOS, CBiCMOS and SBiCMOS.
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---------------
Afternoon Session: 1:30 p.m. - 5:00 p.m.
H.J. Shin, IBM
BiCMOS Digital Applications
BiCMOS Microprocessors, Signal Processors, BiCMOS ASIC Applica-
tions, SRAM/DRAM Applications, BiCMOS Logic Families, BiCMOS
Gate-Arrays.
---------------
Evening Session: 5:30 p.m. - 7:00 p.m.
A. Bellaouar, University of Waterloo
BiCMOS Design : Tutorial II
BiCMOS Subsystem Design Examples, Design Tradeoffs.
---------------------------
Wednesday, April 20th, 1994
---------------
Morning Session: 9:00 a.m. - 12:30 p.m.
B. Leung, University of Waterloo
BiCMOS Analog Design
Analog Basic Circuits in CMOS, Bipolar and BiCMOS, Operational
Amplifiers, Transconductor and other Building Blocks, Circuit
Optimization, High-Performance Design.
---------------
Afternoon Session: 1:30 p.m. - 5:00 p.m.
K. Hansen, Motorola
BiCMOS Analog Applications
BiCMOS Analog Subsystem and System Design, High-Frequency Appli-
cations, Bipolar vs. BiCMOS vs. CMOS and High-Voltage Applica-
tions.
================================================================
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DAILY SCHEDULE:
Morning Sessions:
8:30-9:00 Registration, Course Notes Distribution and Coffee
9:00-10:30 Lecture
10:30-11:00 Break
11:00-12:30 Lecture
12:30-1:30 Lunch
Afternoon Sessions: Evening Sessions*:
1:30-3:00 Lecture 5:30-7:00 Tutorial
3:00-3:30 Break
3:30-5:00 Lecture * Mon. & Tues. only
5:00-5:30 Break
LECTURERS:
A. BELLAOUAR is a visiting Assistant Professor at the University
of Waterloo. He authored and co-authored several papers on BiC-
MOS and CMOS digital circuit design. He is also a co-author of
the book "Digital BiCMOS Integrated Circuit Design" (Kluwer,
1993). His current research interests include applications of
BiCMOS for digital circuits and circuit techniques for low-power
dissipation.
M.I. ELMASRY is a Professor at the University of Waterloo, Direc-
tor of its VLSI Research Group, Fellow of the IEEE and holder of
the NSERC/BNR Research Chair in VLSI Design. He has 30 years
experience in digital IC design and has led a research team for
the last 10 years on BiCMOS digital design. He is a coauthor of
a book and has many publications on the subject.
K. HANSEN is a senior member of the Technical Staff and Lab
Manager of the Integrated Circuit Technology Center for the Land
Mobile Products Sector of Motorola. He has 17 years of experi-
ence in bipolar, CMOS, and BiCMOS analog and digital design for
communications circuits. He holds 7 U.S. patents, has authored
several publications, and is a member of the IEEE.
B.H. LEUNG is an Associate Professor at the University of Water-
loo, Senior Member of IEEE, Technical Committee member of IEEE
CAS and a principal researcher of ITRC, Ontario. His main
research interest is in CMOS and BiCMOS analog integrated cir-
cuits, in particular for data acquisition applications. He
received the BSc. (RPI, '79) MSc. (Caltech, '80) and PhD. (Berke-
ley '87), all in electrical engineering. From 1980-1983, he was
with Northern Telecom, Canada as a circuit designer.
P. KEMPF is manager of IC process R&D at Northern Telecom,
responsible for device formation. He has experience in the
development of several mixed-signal BiCMOS technologies, high-
voltage transistors, EPROM for mixed-signal CMOS processes, and
opto-electronic devices. His research team is currently working
on deep sub-micron mixed-signal BiCMOS and bipolar technologies
for telecom applications.
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J.D. KENDALL is a member of scientific staff at Northern Telecom
in Ottawa. His background includes both bipolar and MOS transis-
tor modeling and parameter extraction, and he has applied this
device background to the modeling and development of BiCMOS tech-
nologies. He has published in the areas of bipolar and MOS
transistor modeling and characterization, and BiCMOS technology.
H.J. SHIN is a research staff member/manager at the IBM Thomas J.
Watson Research Center, Yorktown Heights, NY and Senior Member of
the IEEE. He has 15 years involvement in MOS bipolar, and BiCMOS
digital IC design, including microprocessors, memories, and
high-performance circuits for computers and communications. He
has been active on BiCMOS digital circuits for the last 5 years
and has published several papers on the subject.
REGISTRATION FORM
Name:...........................................................
Membership: (IEEE, ICR or ITRC).................................
Organization:...................................................
Address & City:.................................................
State/Province:................................................
ZIP/Postal Code:................................................
Telephone: ( )................................................
Fax: ( )......................................................
E.mail:.........................................................
Method of Payment (payment must be enclosed with the registration
form before MARCH 1st, 1994)
____ Cheque made payable to "University of Waterloo BiCMOS" in
the amount of $1,350.00 CDN OR $1,147.50 CDN.
Amount CDN $_________.
(Check one) ___Visa ___MasterCard ___American Express
Card #:.........................................................
Expiry Date:....................................................
Signature:......................................................
Mail to:
Mrs. Joan Pache
VLSI Research Group
University of Waterloo
Waterloo, Ontario, N2L 3G1 Canada
--
================================================================================
Joan Pache
VLSI Research Group jpache@vlsi.UWaterloo.ca
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