🚀 go-pugleaf

In <1991May29.153729.23596@gmuvax2.gmu.edu> xwang@gmuvax2.gmu.edu (Xiang-Min Wang) writes:

>just wonder what is the purpose of this group? thank you.

>xwang

The name should give at least a hint. This group is intended to deal with
all aspects of testing/verification of electronic (not necessarily digital
& integrated) circuits. Although there are already a number of groups in the
comp.lsi tree I myself felt that these groups are not a suitable forum for
discussing test aspects & problems. Comp.lsi and comp.lsi.cad (which are
nearly the same, because of continuous cross-posting) are frequently (?)
used for design questions. I expect that designers have not very much interest
in discussing aspects of fault models, fast fault simulation, test generation
algorithms etc. For the designer simulators and test generators as well as 
circuit synthesizers and routers are just tools (this is the industrial
aspect, not the academic). 
A tester, however, has to deal with the "something" s/he gets, and has to 
select an appropriate strategy and tool. Improvement of strategies is here
a main goal.
Although there is an overlap between designers and testers, they usually
speak a different language; and this is why there was a call and vote for
this group.
This has nothing to do with "let's create another group" or "split this
group because of too much volume". Several people remarked that we should 
"first fill up comp.lsi before we build another group". This comes close to
the proposal to fill a bottle with water, coke, beer, whisky etc. and if it
is full take the next one. There is no damage in having another group with
different interests in the USENET tree; there are already ~1250. If you dislike
this opinion, use the unsubscribe feature of your newsreader.

But back to the original question:

After internal and external discussions (e.g. on several conferences) the
conclusion was to propose this group. We have seen this from the academical
point of view and therefore proposed discussion topics like the following:

- information on conferences and workshops (call for papers/participation)
- recent results of research (to be published)
- questions and answers on strategies and algorithms
  - fast fault simulation
  - ATPG
  - analog circuit testing
  - design for testability
  - scan testing
  - random testing
  - fault modelling
- public available software
- discussion on standardisation, e.g. IEEE 1149.* (boundary scan)
- information on new books and journals
- FAQ
- ... (fill in what you think that has to said on 
       testing/verification/fault tolerance ...)


Hope this is sufficient for a first overview.


Holger

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|  |   / Holger Veit             | INTERNET: veit@du9ds3.uni-duisburg.de
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