🚀 go-pugleaf

In article <veit.676191831@du9ds3> veit@du9ds3.uni-duisburg.de (Holger Veit) writes:
>
>Some of the ISCAS'89 benchmark circuits were created by a synthesis
>algorithm from a high level description. Examples are s208, s838, s344
>and (probably) s1423. Some of them also have a distinct "function" that can
>be expressed by few statements in a HL form. Examples are again
>s208 (8 bit programmable clock divider), s838 (32 bit version of s208) and
>s344 (4x4 Bit shift&add multiplier).

Also:

s420	- 16-bit version of the clock divider (the circuit description can be
	  found in "Intro to Computer Logic" by H.Troy Nagle et al. Prentice
	  Hall 1975, p. 461.  Signal W is the carry-out from the counter.
	  Other signals are as in the book.
	  I have descriptions of s208, s420, and s838 in a Pascal-like
	  structural/functional language LOGIC-3, with comments.

s953    - this is a controller taken out of a chip designed at Duke Univ.
	  I might be able to retrieve its description in LOGIC-3, but it
	  will take some time to go through the archival tapes (the chip went
	  through several design iterations and, at the first glance, I can't
	  seem to find the one used for the benchmark...).

s349    - same as s344, except has a couple of redundancies.

I believe that for a couple of other circuits (s1494 and s1488), we have
transition tables of the FSMs - I'll have to check it.

Also, I'll relay the request for HL-descriptions to the contributors of the
benchmarks.

I'll have some more info after DAC ...

KK
-- 
Kris Kozminski   kk@mcnc.org
"The party was a masquerade; the guests were all wearing their faces."