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Article #132

Re: IC Defect Statistics

#132
From: sheldon haynie
Date: Tue, 26 Jan 1993 13:18
71 lines
3537 bytes
in previous post Gerald M. Spiegel says:
	>Anyone who deals with product quality and yield 
	>of integrated circuits probably has the same problem:
	>Where can I get realistic data about defect densities
	>and defect size distributions concerning a certain
	>manufacturing process? Well, so do I.

	>For my opinion, we should stick together and share 
	>the little information we have.
	>So here is my call: Please email ANY information 
	>you have about defect statistics, if you think it
	>might be usable. 
	>No, you are not asked to let out any internal 
	>company affairs, because the information shall 
	>be summarized and posted.

	>Any help is greatly appreciated.

Here's some info from previous processes that I have known well. These
data are 3-15 years old and *should* be therefore pessimisitic estimates. 
Don't ask which fabs, because it doesn't matter. These were all reproducible 
manufacturing numbers, in companys from Fortune 500 to start-ups. Obviously,
*Yield* must be separated from *defect density* by a coherent strategy
that eliminates testing, parametric and design issues. With SRAM or DRAM 
cells, or by arbitrarily grouping adjacent linear die you can synthesize enough
yield vs area information to develop a curve. Take *lots* of data
(> 10,000 wafers) before you decide what your D and Alpha are.


In 1988 I was priviliged to attend a Defect reduction course at RPI
with a presentation by Dr. Stapper... he put up sanitized data that
showed the IBM General Tech. Divisions Historical Defect reduction on a 
log scale. The units were arbitrary, but the slope was near constant from 
'69 to '86...

Model parameters are for a "Stapper" gamma function defect distribution
which fit my data better than exponential, Murphy/Moore or Seeds. Your milage 
will vary. Note: defects do cluster, the distributions are not simple.

Stapper's eqn: Yield = (1 + AD/alpha)^-alpha
where alpha is the parameter for wafer to wafer variations

 
Technology	Design	Feature	Wafer 	D(/cm^2)	Alpha	Tooling
________________________________________________________________________
Bipolar slm 	Linear	5 um 	100mm 	2.5		1.3	PE 341
Bicmos	dlm	Linear	3	100	1.02		.8	PE 341
CMOS	slm	digital	5	100	10		3	Canon Prox.	
CMOS	dlm	digital	2	100	5		3	PE 341	
CMOS	dlm	digital	1	100	3		2	5:1 DSW
Bicmos	dlm	linear	2	100	10		3	5:1 DSW
DMOS	slm	disc.	4	100	8		2	Canon Prox.
DMOS	dlm	disc.	5	75	7		2.5	Canon Prox
JFET	slm	disc.	2	50	20		.3	K&S contact
Bipolar	slm	disc.	10	75	50		.5	K&S contact

Notes: 	slm = single metal
	dlm = double metal
	The tooling and possible redundancy of the circuits will dramatically
	affect yields... Note that the contact printers (ca 1978) with 
	emulsion masks gave very consistent (small alpha) results.
	
Sheldon Haynie		|
Unitrode IC Corp	| 
7 Continental Blvd.	|
Merrimack, NH 03054	|
FAX:603-424-3460	|voice:603-424-2410 (EST)|	sdh@.uicc.com
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Newsgroups: comp.lsi.testing,comp.lsi,comp.lsi.cad
Path: arc1-ca.pugleaf.net!sparky!uunet!usc!sol.ctr.columbia.edu!eff!world!mv!chillon!sdh
From: sdh@uicc.com (sheldon haynie)
Subject: Re: IC Defect Statistics
Message-ID: <1993Jan26.131830.19721@uicc.com>
Summary: IC defects and yields
Keywords: yield, defects, models
Sender: news@uicc.com (USENET News System)
Organization: Unitrode Integrated Circuits Corp., Merrimack, NH, USA
References: <1jp137INN2gj@iraul1.ira.uka.de>
Date: Tue, 26 Jan 1993 13:18:30 GMT
Lines: 71