🚀 go-pugleaf

Has anyone utilized JTAG boundary scan to perform tests of system logic?
Specifically, I would like to do the following:
1) Scan in test data along the boundary scan register.
2) Allow the system to run for one clock cycle using data from the boundary
scan register as input to the system logic.
3) Record the system outputs in the boundary scan register.
4) Scan out the results.

My problem is with steps 2) and 3) above.
If I use the Internal test, how do I allow the sytem to run for one clock
cycle? Since the system clock is an input, it is unavailable. Do I simply
let the system run for one cycle of TCK in the Run-test/Idle state of the
TAP controller. Is there another way to do this without using the Internal
test? Perhaps using the Sample test in conjunction with external system
clock controls?

Any help/pointers/suggestions would be greatly appreciated!

Anthony Sama
Drexel University