🚀 go-pugleaf

In article <DON.ALLINGHAM.92Sep3081939@bbking.FtCollins.NCR.COM> Don.Allingham@FtCollinsCO.NCR.COM writes:
|From what I see, the problem is reversed, especially among ASICs.  Maybe
|not for DRAMS, SRAMS, or other stable, long term processes.  In the ASIC
|market, the processes are always on the leading edge.  You have to be,
|or you cannot stay in business.  Everyone wants the leading edge process
|because it is denser (cheaper) and faster.  New processes are always
|less stable than old, mature processes.
|
|--
|Don Allingham           
|NCR Microelectronics 			Don.Allingham@FtCollins.NCR.com
|Ft. Collins, CO.        		uunet!ncrlnk!ncr-mpd!Don.Allingham
|

Just a comment, not everyone wants the leading edge process.  For a majority
of consumer products, the cheapest most mature process is perfect.  This
seems to hold pretty true for medium size multipliers (500k - 1M parts) esp
when the design is pad limited.


Obligatory test statement.
Test issues are growing in complexity because of technological strides and 
an increased emphasis on product quality and reliability. As designs sizes 
increase beyond 40k gates, ad-hoc DFT techniques along with traditional test 
pattern generation methods no longer provide high fault coverage for any 
given design, without the designer or test engineer manually generating a 
majority of tests.  Along with these pressures, the market place is also 
demanding that products are completed faster and with less cost. The goals, 
however, are a trade-off between two seemingly divergent concepts, reduce 
testing costs and increase product reliability.


Subhash
roy@mcnc.org
"Yet another IC designer from MCNC"