🚀 go-pugleaf

Holger> I cannot imagine that everyone is interested in design
Holger> (comp.lang.vhdl, comp.lang.verilog, comp.sys.mentor, comp.lsi*),
Holger> but nobody in testing of all the stuff produced. 

Unfortunately, this seems to be the view most seem to have.  Many
designers seem to think test is something that can be held off until the
end or "thrown over the wall" to someone else.  *Many* designers do not
think about test at all.  They use no structured test (BIST, scan, JTAG)
and do not even fault grade, but assume that a few functional tests will
ensure that their 30,000 gate circuit works properly.  You can usually
tell who the really experienced designers are.  They are the ones who
are worried about test up front.

I believe that this can be traced back to universities.  I had many
classes dealing with design, from the transistor level to the system
level.  My total exposure to test was a 50 minute lecture that briefly
touched on LSSD.  If I had not been in a cooperative education program,
I would have shared the misconception of many of my classmates who
assumed that every die on a wafer was good.

Hopefully, someday all designers will realize that test needs to be
considered up front, and that no tool exists that will generate 100%
stuck-at fault coverage without modifying their 50,000 gate asynchronous
design. 

Thank you.  I will now step off my soap box.

--
Don Allingham           
NCR Microelectronics 			Don.Allingham@FtCollins.NCR.com
Ft. Collins, CO.        		uunet!ncrlnk!ncr-mpd!Don.Allingham