🚀 go-pugleaf

Following the new birth of this news group, here is some
chest thumping regarding ICCAD-92.  It was mailed to a variety
of commercial magazines and newspapers, so it contains more than
the usual amount of hype.

For those of you that need to write trip reports, here is your
chance to write the report before you go to the conference!

For those of you looking for controversy, check out the panel 
session description entitled 

  "University Faculty:  Visionaries or Mercenaries ?"

Kent
fuchs@crhc.uiuc.edu
Univ. of Illinois

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                       CONFERENCE OVERVIEW

        INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN

                            ICCAD-92

     The Tenth International Conference on Computer-Aided Design,
ICCAD-92,  offers  an  exceptionally  strong  schedule of papers,
tutorials, and vendor suites.   The program promises to challenge
experienced  CAD  developers,   hardware  designers, and academic
researchers who want to learn from the latest in CAD research and
development.

     ICCAD-92 will be held November 8-12, 1992 in the Santa Clara
Convention  Center,  Santa  Clara,  California.   The  conference
concentrates on CAD for electronic design and features three days
of technical sessions, one day of four different tutorials, and a
lively evening panel discussion.   To  complement  the  technical
program,  numerous  CAD  vendors  will  have  suites at ICCAD-92.
This offers the conference attendees a unique opportunity to hold
in-depth  technical  discussions  with  vendors  on  their latest
products.

                       TECHNICAL SESSIONS

     The  heart  of  the  conference,  the  technical   sessions,
includes   a  total  of  over  110  papers.    The  presentations
represent the latest in CAD work from  industry,  research  labs,
and   academic   institutions.    A  sampling  of  papers  deemed
exceptionally noteworthy by the technical  program  committee  is
included  in the following discussion.   The reader is encouraged
to  consult  the  ICCAD-92  Advance  Program   for   a   complete
description of sessions, paper titles, and authors.   The Advance
Program can be obtained by contacting the conference  management,
MP  Associates,  via phone or FAX as described at the end of this
conference preview.

Synthesis

     Logic and behavioral synthesis continues to  be  a  research
area  exhibiting  rapid  progress,  with  many  papers  reporting
important results at this year's ICCAD. There are several  papers
on  the  use  of  synthesis techniques for reducing circuit power
requirements.   A paper from  Berkeley  and  NEC  in  session  6C
describes  the  use  of  architectural  transformations for power
minimization.  Chandrakasan,  Potkonjak,  Rabaey,  and  Brodersen
propose  five  groups of architecture transformations appropriate
for reducing  power  requirements.   Their  experimental  results
indicate  that  an  order  of magnitude reduction in power can be
achieved in some cases over  current-day  design  methods,  while
maintaining  system  throughput  and  implementation area.    The
relationship  between  signal   transition   probability,   power
dissipation,  and  random  pattern  testability  is explored in a
paper by Ghosh, Devadas, Keutzer, and Shen  of  Mitsubishi,  MIT,
and Synopsys.   They show how synthesis techniques can be used to
modify signal probabilities and thereby  improve  random  pattern
testability as well as reduce average-case power dissipation.

     A number of presentations at ICCAD will present  results  on
synthesis of sequential circuits.    The notion of false paths is
extended from combinational to sequential circuits by Ashar, Dey,
and  Malik  of  NEC  and Princeton.  In session 10C they show how
multiple-cycle  false  paths  can  be  removed  from   sequential
circuits in order to enhance circuit performance using techniques
similar to those previously developed for combinational circuits.
Session  3C  contains  a  variety  of new results on synthesis of
asynchronous circuits.    A new unified signal  transition  graph
model  will  be  presented by Yakovlev, Lavagno, and Sangiovanni-
Vincentelli of Berkeley and the Univ.  of  Newcastle  upon  Tyne.
Their   model   provides  for  the  precise  characterization  of
classical static and dynamic hazards.

     Hardware/software  co-design  is  included  in  this  year's
ICCAD.  Papers  in  session  10B  describe  results on the use of
synthesis  in  assisting  in  the   hardware/software   co-design
process.     As  an example, Chou, Ortega, and Borriello from the
University  of  Washington  will  describe   an   algorithm   for
synthesizing  the  hardware/software interface in microcontroller
applications.    Example results using their synthesis tool  show
circuits  and driver code that is comparable to that generated by
human designers.

Testing

     Five sessions of ICCAD-92 are devoted to test generation and
design  for testability.   Particularly hot topics with important
results to be presented include test generation for delay faults,
architecture-level test generation and synthesis for testability,
and test generation for sequential circuits without scan.

     Session 11B includes two papers on testing for delay faults.
Delay  fault  test  generation for sequential circuits has in the
past been a particularly difficult problem.  The paper  by  Cheng
of  AT&T  describes  a  method of delay fault test generation for
both non-scan and partial scan sequential circuits.   He  uses  a
new  fault  injection  technique which allows a modified stuck-at
sequential test generator to create tests for transition  faults.
The  results  in  the  paper  by  Pomeranz  and  Reddy  from  the
University of Iowa in  the  same  session  include  a  method  of
estimating  path-delay  fault coverage.   The complexity of their
approach is polynomial in the number of lines in the circuit, and
thus  allows  circuits  with  a  large  number  of  paths  to  be
considered.

     Behavioral testability analysis and synthesis is  the  focus
of  session  12B.   The  paper by Lee, Wolf, and Jha of Princeton
describes a method for improving  testability  during  data  path
scheduling.    Their benchmark examples show high fault coverage,
short test generation time, and low area overhead.  Reduction  of
test   application   time   is   the  problem  addressed  in  the
presentation by Narayanan, Gupta, and Breuer of  USC  in  session
2A.   They  describe an algorithm to optimally construct multiple
scan chains to reduce the overall test time.  The  main  idea  of
their  approach  is  to  assign those scan elements that are more
frequently accessed to shorter scan chains.    The  algorithm  is
based  on  dynamic  programming  and  they  demonstrate test time
reductions  as   large   as   40%   over   equal   length   chain
configurations.

Field Programmable Gate Arrays

     FPGAs play a prominent role  at  ICCAD-92.    The  lead  off
technical  session  on Monday includes a tutorial presentation on
FPGAs  as  well  as  two  papers  on  look-up  table  based  FPGA
synthesis.    Cong and Ding from UCLA describe how the technology
mapping problem for depth minimization in  FPGAs  can  be  solved
optimally in polynomial time for general Boolean networks.  Their
experimental results show reductions in  network  depth  and  the
number   of  required  look-up  tables.  Interesting  methods  of
patching FPGA designs are presented by  Fujita  and  Kukimoto  of
Fujitsu  and  the  University of Tokyo.   Instead of changing the
netlist due to a design modification, they modify  the  functions
realized  by  look-up  tables in order to not change the delay in
the patched circuit.

Formal Hardware Verification

     The challenging and difficult circuit  verification  problem
will be examined by four papers in session 4C.   Macii, Plessier,
and Somenzi from the University  of  Colorado  have  developed  a
method  of  verifying  systems containing counters.   They verify
tasks  that  express  both  safeness  and  liveness  constraints.
Redundancy  removal is an important element in their verification
procedure.  Another paper in the same session describes  the  use
of  CTL  logic  to  verify  a  system of interacting finite state
machines.   Chiodo, Shiple, Sangiovanni-Vincentelli, and  Brayton
of   Berkeley   and   Magneti  (Italy)  apply  property-dependent
reductions  to  the  components  before  building   the   product
machines.   They  are  able to verify a wide class of properties,
including liveness constraints.

     In addition to logic verification, the problem of  verifying
clock  schedules  is  also  addressed  in this year's conference.
Several recent papers have formulated timing  verification  as  a
mathematical  programming  problem.    Szymanski  from  AT&T  and
Shenoy from Berkeley will present results at ICCAD that show  the
accuracy  and  complexity  of  previous  algorithms  may  not  be
acceptable.   As an alternative, they present a simple polynomial
time  algorithm  for  clock  schedule  verification.    In  their
experimental timing verification of the ISCAS benchmark  circuits
the observed running times are linear in circuit size.

Simulation

     New  applications  and  approaches  to  circuit  and  system
simulation   continue  to  appear.     At  ICCAD  there  will  be
presentations  on   methods   ranging   from   probabilistic   to
compiled-code   simulation   with   applications   varying   from
transmission lines to power  estimation.   Bracken,  Rohrer,  and
Raghavan  from  Carnegie  Mellon  University  have  extended  the
asymptotic  waveform  evaluation  technique  to  the  generalized
method of characteristics.   The resulting model is more accurate
than previous approaches at lower orders of approximation and  it
can  be  simulated  efficiently in the time domain, together with
linear and nonlinear elements.

     Session 8A is devoted to high performance  simulation  using
both  new  simulation  algorithms  and  new  simulation hardware,
including data flow architectures.    Included in that session is
a  paper  by  Shriver   of  DEC and Sakallah of the University of
Michigan on compiled-code logic simulation.   Their simulator  is
suitable   for   both   functional  and  timing  verification  of
multiphase synchronous circuits.   It  is  based  on  a  waveform
model  of  synchronous  operation  and  an associated algebra for
combining such waveforms both logically and temporally.

     As an  alternative  to  full  circuit  simulation,   several
papers  will  introduce probabilistic and statistical methods for
estimating specific circuit properties.  Li, Stamoulis, and  Hajj
from  the  University  Illinois  describe  a probabilistic timing
technique with applications  to  hot-carrier  effect  estimation.
The  probabilistic  simulation provides for the evaluation of the
cumulative effects of all input waveform combinations in one run.
In  a  paper by Burch, Najm, Yang, and Trick of Texas Instruments
and the University of Illinois, Monte Carlo techniques  are  used
to  estimate circuit power consumption.  The statistical approach
provides the speed of probabilistic techniques with the  accuracy
of simulation.

Analog CAD

     Several papers describing the notable progress of  computer-
aided  analog  design are included in the conference program.   A
paper  from  the  Swiss  Federal  Institute  of  Technology  will
describe  a  symbolic  approximation method for generating analog
circuit analysis equations.  Seda, Degrauwe, and Fichtner show  a
two  order-of-magnitude improvement on large circuits as compared
with traditional full expansion  techniques.     Their  technique
uses  numeric  information  to guide the symbolic manipulation in
order to avoid unnecessary work and save memory space.

Frameworks and Design Representations

     Design management is an important, but sometimes  forgotten,
aspect  of  CAD  research.   ICCAD-92 has devoted two sessions to
design management and representations.   A paper  describing  the
integration of design flow with a framework based CAD system will
be presented by Bingley, Bosch, and van der Wolf from  the  Delft
University  of  Technology  in  session  11A.    They address the
interface  between  the  design  tools  and  the  framework,  the
architecture  of the framework, and the internal operation of the
flow management components.    Graphical  representation  of  the
design  flow  configuration  is  used  as  the  basis  for design
actions.   A paper from Motorola by Vasudevan, Mathys, and  Tolar
will describe how they implement a design tracking system.   They
adopt what they call an observer  and  lightweight  architecture.
The  argument  is  made  in the paper that observer architectures
provide the same benefits as  controller  architectures  but  are
much more politically correct from an industry viewpoint.

                          PANEL SESSION

     The panel for ICCAD-92  follows  the  same  format  as  last
year's  highly interesting and at times controversial discussion.
The title of the  panel  organized  by  Bill  Joyner  of  IBM  is
"University  Faculty: Visionaries or Mercenaries ?". Increasingly
university faculty serve on advisory boards of corporations,  act
as  consultants,  and  sometimes  establish and operate their own
companies, while maintaining their university status.   They have
varying    degrees   of   connection   with   several   companies
simultaneously.   Research contracts may  involve  not  only  the
development  of research results, but the delivery of hardware or
software to be incorporated into products.

     Members of the panel from industry and academia will present
a  variety  of  perspectives.   The  presentations  promise to be
entertaining and controversial as the panelists address a variety
of  questions.    Will  long  term  research  at  universities be
subordinated to short term deliverables? Is the education process
hampered  by  these  entangling alliances, or do students benefit
from exposure to real-world  problems?     Are  the  scholar  and
entrepreneur inextricably linked?


                            TUTORIALS

     This year there will be four different tutorials on the last
day  of  the  conference,  Thursday, November 12.   Attendees may
register for any one of the full-day tutorials.

     The  tutorials   are   on   Multi-Level   Logic   Synthesis,
Interconnect  and  Packaging  Analysis,  Introduction to Embedded
System Design, and Architectures for Software Systems.

     It is important to register early for  the  tutorials  since
attendance  is  limited  and  all sessions are likely to be full.
Tutorial registration information is included on the registration
form  included  with  this preview.  More detailed information is
contained in the Advance Program.


           ADVANCE PROGRAM AND CONFERENCE INFORMATION

     The Advance Program and detailed information  regarding  the
conference  can  be  obtained  by  contacting  the conference and
vendor suite management via phone or FAX:

MP Associates
7490 Clubhouse Road
Suite 102
Boulder, CO  80301
Telephone: (303) 530-4562
FAX: (303) 530-4334

                          REGISTRATION

     A discounted advance  registration  has  been  provided  for
those  that  send  in their registration before October 12, 1992.
On-site registration will also  be  provided  at  the  conference
site,  the  Santa  Clara  Westin  Hotel and adjoining Santa Clara
Convention Center.  Registrants desiring a specific tutorial  are
advised  to  register  early since attendance in the tutorials is
strictly limited.   For those only wishing to attend  a  specific
day of the conference, a reduced one day only registration option
has been provided.   Registration can be made by  completing  and
mailing  in  the  conference  and  hotel registration forms or by
completing the forms in the Advance Program.