🚀 go-pugleaf

For those who see the light and decide that testing
is necessary, there are still a number of questions
regarding WHAT to test and HOW MUCH to test. This
is from a design engineer's point of view.

The majority of companies/managers/engineers that
believe in testing simply invest in an ATPG tool
that generates tests for single stuck-at faults. There is usually very
little consideration given to
real defect modes in real chips and how these defects map into various
fault models (stuck-ats,
bridging faults, transistor gate open, etc.). 

It is difficult to know exactly what defect modes
to test for (and what fault models to use in order
to reasonably cover these defects). Even if one
decides on fault models somehow, getting proven ATPG
tools that can cover those faults directly or
indirectly is quite difficult. Even if appropriate
ATPG tools can be found, getting the ASIC vendor
to accept "non-standard" test vectors (such as
delay fault testing using scan, or IDDQ testing)
is a difficult task in general.

Thus, most people settle for some kind of scan
structure (full/partial) and a stuck-at fault
model, because that is the easiest thing to do.
Fault coverage in the high 90's makes people feel
good about what they have done, especially when
they hear from the foundry that 60% of the chips
from a lot didn't pass the scan tests.

Then comes the question of how much to test. Design-
for-test typically comes at a price (area,timing),
but DFT is usually necessary to keep fault coverage
high. How much fault coverage is good enough,
especially when one uses a stuck-at model and does
not know what real defects are being covered ? Note
that process yield is also unknown most of the time.




-Kumar Venkat

 Silicon Graphics, Inc.
 (415) 390-5320
 kumarv@sgi.com