🚀 go-pugleaf

In article <BxD9CM.C1@scd.hp.com> vinoski@ch.apollo.hp.com (Stephen Vinoski) writes:
>
>One issue with 1149.1 is that every chip has its own scan controller.
>This is fine for chip test, but for board test it would better if
>there were only one controller for all the chips on the board.  See
>
>	Dervisoglu, B.I., "Scan Path Architecture For Pseudorandom
>	Testing", IEEE Design & Test of Computers, 6(4): pp. 32-48,
>	1989.
>
>	Dervisoglu, B.I., "Features of a Scan and Clock Resource Chip
>	For Providing Access to Board-Level Test Functions", Journal
>	of Electronic Testing: Theory and Applications, 2: pp.
>	107-115, 1991.

There is not one scan controller per chip.  There is one TAP controller
for each chip that has boundary scan implemented.  All chips do not
need to implement boundary scan, and seldom - if ever - do you find a
board where they all do.  Depending upon the implementation, there may
be a scan controller on the board, but usually not.  Scan control is
implemented in a computer that has a scan control chip (usually -
though this can be done in SW), and SW used for testing and diagnosis.

NOW...  I WANT TO TAKE EXTREME ISSUE WITH YOUR INFERENCE THAT THE
APOLLO 10K ARCHITECTURE FOR SCAN IS SOMEHOW BETTER THAN BOUNDARY SCAN.

The P1149.1 standard is the engine that is driving the future of
built-in test.  Departures from this standard slow the process of
progress.  The issue is not whether something is better (and I doubt
that your example qualifies) but whether the standard is "good
enough".  If it is good enough, it should be used, and if it is used
people will find that it has much more capability than is visible on
the surface.  For example, did you know that ATT uses boundary scan as
the basis for communication of internal BIST results from chips to
boundary scan controllers in production test applications?  Did you
know that this use, and extensions of this methodology, are in
development at many major sites in the US and elsewhere?

Did you know that a substantial infrastructure - involving HW and SW is
being created around P1149.1 and its extensions, an infrastructure that
will not support other architectures and scan methodologies?  Do you
think it is smart and cost effective and productive to depart from the
standard under these conditions?

Arnold Frisch
Tektronix Laboratories