🚀 go-pugleaf

>So Doug, While I'm trying to formulate my next question, let's hear 
>one from you!  Have you had any 1149.1 implementations tossed your way
>in board test.  Did your testers handle the task.  Who wrote the b-scan
>test vectors?  Did you have any internal scan paths?  Multiple paths?
>What where the major hurdles?  Did anything go completely wrong?
>
>Anyone else...?
>
>Ed Kearns

Ed:
So far we haven't had any 1149.1 designs come our way. I don't think
that the design guys in NASA have really gotten into it yet... they
are using XiLinx and Altera stuff to keep us pretty busy and I'm not
sure that if they started using 1149.1 chips whether they would write
on-board code for BIT or just for us board test people to crank out 
quicker tests. BTW, our board test equipment is being used for depot /
interlevel repair of broke boards that used to work. So 1149.1 tests
would be good for getting up a quick test of the board, but later 
(as time allows or testing requires) it would behoove us to write a 
more complete test. The built-in RAM tests that HP provides with the
tester tests a minority of addresses, and while that ok for the 
manufacturing environment looking for incorrectly mounted or dead chips
in quick test time, doesn't provide a thorough test in the depot 
environment.

Major hurdles? Getting design to put in gates to disable ttl
oscillators... :^) ... no flame intended. All things considered
we actually have a pretty good rapport with the design people.

Regards, Doug

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+-----------+---------------------------------+--------------------------+
| Doug Reed | HP3065AT Board Test Engineering | Kennedy Space Center, FL |
| Ham Call N4QVY | #include <std_disclaimer> | Lockheed Space Operations |
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