1149.1 for Xilinx FPGA's

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1 total messages Started by Michael Haney Fri, 24 Jul 1992 19:39

#12

Author: Michael Haney
Date: Fri, 24 Jul 1992 19:39

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Does anyone have an 1149.1 implementation for the Xilinx 3k
family that they would be willing to share?

Specifically, I am thinking about putting boundary scan into
an XC3042-based project that I am working on, and I am curious
as to how many CLB's it will cost for the controller and the
boundary cells.

I don't want to use Xilinx's configuration readout; I wish to be
JTAG compliant with other devices in the project...

Any information would be welcome.

Mike Haney
haney@cs.uiuc.edu

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