🚀 go-pugleaf

I think Janak Patel has pointed out an important question which may have
to be answered before talking about testing issues. Also, do test
engineers really hype the need for test?

> Janak> In this sense, testing is like buying an insurance.

I compare test to an "extended warranty" rather than "insurance". An
insurance policy is bought to protect oneself from the external 
environment whereas an extended warranty or even a "guarantee" is a 
protection against defective products.

> Janak> Designers don't see any concrete gain by adding in 
> Janak> testability - it just comes in their way!

This reminds me of a talk given by Dr. Szygenda at the "First
International Workshop on the Economics of Design, Test and
Manufacturing". He focussed on the legal aspects of not testing designs. I
remember him saying that, legally a design engineer can be held responsible
for a defective design (we all know that defective manufacturing can
result in problems -- automobile recalls, defective medicines etc.) and
can be potentially sued by a customer!! If in the future, in fact
customers start suing system developers and system developers in turn sue
the chip makers [I am sure the lawyers will try to find a way out of
it;-)], testing can easily become a tangible thing. Do you think if a
design engineer is told that he can be the target of a law suit if he did
not consider testing :-), he will still say, "I am not interested in
testing the design"? Just look at the US doctors and you will know the
answer.

> Janak> If you can't think of such a chip, look up a $1 LCD watch.

The less expensive an item is, the lower are the chances that a customer
is upset with the product [my experience, of course:-)]. That is why such
products allow you take risks. But, just think of buying a $15,000 car and
finding out that it has a defective chip which proves to be fatal within
one month of purchase. The customer will sue the auto maker who in turn
will definitely pass that on to the chip maker and so on. 

> Janak> It is very hard to sell testability or high coverage to this group.
> Janak> (a) you don't ship very many defective chips. (just lucky!) or

It is tough to argue with luck. I will run through a red light today and
TEST my luck. See, you even have to TEST your luck;-)

> Janak> (b) the customers are not very mad at receiving bad chips, or

This might depend upon how frequently they receive the bad chips. If it is
too often, it is hard to believe that the companies can still maintain 
their supremacy in a competitive market.

> Janak> (c) the customers don't know that it is your chip that is bad in
> Janak> the board.

This is dangerous territory. Either they will have to improve the board
tests or just hope that they are lucky that their customers buy their
board and never use it:-)

So, it looks like the best case just works on luck (I too have heard this
reason very often, although in secret) and if this is the case, I am 
surprised why companies are starting to panic to find better testing 
strategies [if not, wake me up:-)]. It is understandable if companies do
not want to spend money on extensive testing, but there needs to be at
least some amount of testing (how much is the question) to ensure quality.

If the customer answers the question, "To sue or not to sue", then I will
answer the question, "To test or not to test":-) 

Praveen Vishakantaiah.

------------------------------------------------------------------------------
-- Microelectronics and Computer Technology Corporation, | Ph : (512)338-3736|
-- 3500 W. Balcones Center Drive                         | e-mail :          |
-- Austin, TX 78759.                                     | praveen@mcc.com   |
------------------------------------------------------------------------------
-- ALSO A HARD WORKING MEMBER OF :-)                     |
-- Computer Engineering Research Center,                 | Ph : (512)471-8013|
-- University of Texas, Austin.             e-mail : praveen@cerc.utexas.edu | 
-----------------------------------------------------------------------------

In article <17lsueINN1js@bashful.crhc.uiuc.edu> patel@crhc.uiuc.edu (Janak H. Patel) writes:

>   For high yield (very close to 100%) parts, the answer is very clear,
>   "I hardly ever ship a defective part, so why do I need testing?"
>   In reality, this does happen.  I know two manufactureres who do not
>   test some chips.  These chips are high volume, mature process, and
>   very low cost.  Any testing would just increase the cost. (one also
>   told me that testing would increase defects in such a chip!)

I think a lot of this has to do with the part itself.  Maybe a cheap $1
LCD watch that comes from a typical 100% yield process, this would be
ok.  But for an SRAM for a satellite, I would want to make sure I
completely tested it.  Even 100% yield processes have problems.
Suppliers can ship you bad material.  Machines in the fab may glitch.
There are a lot of variables.

>   Then there are chips with low yield, aggressive design and large number of
>   gates, such as microprocessors, where it is very easy to justify
>   testing and testability benefits.

>   However, a vast majority of ASIC designs fall between these two
>   extremes.  It is here where the situation is very murkey.  It is
>   not very easy to sell testability and high coverage to these group.
>   What if you did only a functional test with 60% coverage?

We normally see a trade off.  The major concerns are:

	1) Time to market
	2) Quality
	3) Cost

Pick any two :-)  Design complexities of ASICs have been skyrocketing in
the past few years.  The many ASICs are starting to become 20k, 30k, and
even 50k+ gates in size.

>   Best case is that,
>   (a) you don't ship very many defective chips. (just lucky!) or,
>   (b) the customers are not very mad at receiving bad chips, or

Boy, would I like to have customers like this :-)  I have some land in
Florida for sale ....

   (c) the customers don't know that it is your chip that is bad in the board
       (they may attribute the defect to the board manufacturing process rather
	than to your chip manufaturing process)

But they will eventually find the problem.  And when they do, you can be
guaranteed a very angry customer.  If for some reason, they don't find
the problem, a low yield may make the board unattractive to manufacture,
and it may be cancelled.  The those selling the chips lose, too.

>   The "best cases" defined above are far from rare, in fact some
>   tell me that it is the norm in their facility.  The "worst cases" are
>   rare at present, but are increasing with the size of the ASICs.

From what I see, the problem is reversed, especially among ASICs.  Maybe
not for DRAMS, SRAMS, or other stable, long term processes.  In the ASIC
market, the processes are always on the leading edge.  You have to be,
or you cannot stay in business.  Everyone wants the leading edge process
because it is denser (cheaper) and faster.  New processes are always
less stable than old, mature processes.

--
Don Allingham           
NCR Microelectronics 			Don.Allingham@FtCollins.NCR.com
Ft. Collins, CO.        		uunet!ncrlnk!ncr-mpd!Don.Allingham