🚀 go-pugleaf

It appears to be quite a difficult problem to correctly perform a
Layout Parasitics Extraction ("L.P.E.") for MOS integrated circuits,
at least with the electrical CAD software that I'm familiar with.
I hope that other net readers have also attacked this problem and
can share their traumatic (or triumphant) experiences.

The basic problem is in correctly counting up the lengths of the edges
of conducting wires, AND ASSIGNING EACH EDGE TO ITS CORRECT CATEGORY,
so it can be used in the final capacitance calculations.  For example,
consider the two layouts below; they are identical except that the layers
are reversed:

      polysilicon                           metal-2
  +---------------------------+        +---------------------------+
  |                           |        |                           |
  |                           |        |                           |
  |      +---------------+    |        |      +---------------+    |
  |      |               |    |        |      |               |    |
  |      |               |    |        |      |               |    |
  |      |  metal-2      |    |        |      | polysilicon   |    |
  |      +---------------+    |        |      +---------------+    |
  |                           |        |                           |
  |                           |        |                           |
  +---------------------------+        +---------------------------+

To find metal2-to-poly capacitors, L.P.E. software tends to work like this:
	1. Find the region(s) where metal2 overlaps poly
	2. Count up the area and perimeter of the overlap region
	3. Multiply the area by a user-supplied constant, and multiply
		the perimeter by another user supplied constant.
	4. Add these together for the capacitance from metal2 to poly.

BUT THIS IS WRONG!!!

Why?  We need to distinguish between a poly edge and a metal-2 edge,
but the L.P.E. software can't tell them apart.

The intersection region in the left figure is all metal-2 edges, while
the right figure's intersection region is all polysilicon edges.  Poly
and metal-2 are different in thickness by >3X, so the fringing fields from
their conductor edges are quite different.

Also, in the left figure *all* of the field lines go downward from metal2
to poly, but in the right figure only *part* of the fringing field lines
go upward to metal2; part of the field lines go DOWN TO THE SUBSTRATE.
So the (metal2 to poly) capacitance due to edge effects is different between
the two figures, but the L.P.E. software reports them as the same.
And the software is wrong.

(Of course the general case would probably be something more complicated,
like a pair of arbitrary polygons that overlap in some places and don't
overlap in others, but this simple rectangle example shows the basic problem).

	Now it's fair to ask, Who Cares?  Isn't it possible to jiggle the
	input coefficients so that the worst-case (largest) fringing field
	physical situation is assumed?

	I would offer the answer, "Yes, and this procedure gives capacitor
	outputs which are as big or bigger (maybe a LOT bigger) than the
	real, physical capacitances in the actual layout.  And this is
	an error.  Maybe an error of estimating a capacitance way too high
	is just as damaging as an error of an estimate way too low.  For
	some circuits it's important to minimize the error, not just
	guarantee that the sign of the error is positive."


So I've been attempting various strategies (i.e. sneaky tricks) to fool
assorted Layout Parameter Extraction software packages into counting up
edges individually.

Has anyone else done this?  Successfully?  I'd really love to hear from
you if you have.

A million thanks,
-- 
 -Mark Johnson	*** DISCLAIMER: Any opinions above are personal. ***	
 UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mark   TEL: 408-991-0208
 US mail: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086