Hughes' 3-D Processor Array

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Article #1197

#1197

From: Rod Barman
Date: Fri, 09 Dec 1988 18:38

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I recently read somewhere a blurb about a 32 by 32 processor array
designed at Hughes.  The array is composed of multiple wafers, each one
bit-slice, sandwiched together vertically.
 
If somebody knows of any references, I would appreciate a message.

Thanks in advance,
-- 
Rod Barman, Dept. of E.E., University of British Columbia
CDN : rodb@ee.ubc.ca
UUCP : ..!ubc-vision!ee.ubc.ca!rodb
CSNET : rodb%ee.ubc.ca%ean.ubc.ca@RELAY.CSNET

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!cornell!uw-beaver!ubc-cs!coho!rodb
From: rodb@coho.UUCP (Rod Barman)
Newsgroups: comp.lsi,comp.arch
Subject: Hughes' 3-D Processor Array
Message-ID: <288@coho.UUCP>
Date: 9 Dec 88 18:38:16 GMT
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Organization: UBC Dept. of Electrical Engineering, Vancouver, Canada
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