Re: Hughes' 3-D Processor Array

Article View: comp.lsi

Article #1203

#1203

From: Jaime Moreno
Date: Sat, 10 Dec 1988 23:08

15 lines
984 bytes

The upcoming International Conference on Wafer Scale Integration
(January 3-5, San Francisco) will have three papers on the topic:

	- The 3-D Computer
	- Reliability of the 3-D Computer under stress of mechanical
	  vibration and thermal cycling
        - Redundancy for yield enhancement in the 3-D computer

The three papers are from people at Hughes Research labs.

Jaime Moreno

-------------------------
Internet: moreno@CS.UCLA.EDU
    UUCP: ...!{ihnp4,ucbvax,sdcrdcf,trwspp,randvax,ism780}!ucla-cs!moreno

Technical Details

Message-ID: <18778@shemp.CS.UCLA.EDU>

Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!seismo!sundc!pitstop!sun!decwrl!labrea!rutgers!ucla-cs!moreno

References: <288@coho.UUCP>

Show Full Headers

Complete Article Headers

Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!seismo!sundc!pitstop!sun!decwrl!labrea!rutgers!ucla-cs!moreno
From: moreno@maui.cs.ucla.edu (Jaime Moreno)
Newsgroups: comp.lsi,comp.arch
Subject: Re: Hughes' 3-D Processor Array
Message-ID: <18778@shemp.CS.UCLA.EDU>
Date: 10 Dec 88 23:08:31 GMT
References: <288@coho.UUCP>
Sender: news@CS.UCLA.EDU
Reply-To: moreno@cs.ucla.edu (Jaime Moreno)
Distribution: na
Organization: UCLA Computer Science Department
Lines: 15

Reply to Parent Message