🚀 go-pugleaf

A useful table appeared in EE TIMES, (20 Mar 1980) page T18 --
"Chip sans killer defects".  It provides a relatively unbiased
projection of current and future state of the art in MOS manufacturing
yields.

Basically, chip yield falls off exponentially as (A * D), where A is
the die area and D is a measure of the dirtyness of the fab (the "defect
density").  The article provides values of  D  for various years,
both past and future.  Note that these are just one author's *opinion*
of defect density; tain't necessarily correct.  Nevertheless the
projections are useful for provoking amusing discussions:

Year				1984	1987	1989	1992
Defect density [cm^(-2)]	1.83	1.16	0.72	0.38


If these are correct (a *big* if, not a given at all...) then one can
prognosticate about yields of current and future MOS microprocessors.
Just for a grin, let's look at two different die sizes: a 10x15 millimeter
chip, and a really monstrous big chip having 50% more area at 15x15.
(recall the i860 is 10x15).  Let's assume 6 inch wafers:

                   Defect      # Die sites on      Percent     # Good
Die        Year    Density     a 6-inch wafer      Yield        Die
-----------------------------------------------------------------------
10x15      1987    1.16/cm2         85              18 %         15
10x15      1989    0.72/cm2         85              34 %         28
15x15      1987    1.16/cm2         49              7.4 %         3
15x15      1989    0.72/cm2         49              20 %          9

So we can see that right now, today, 1Q-1989, the industry ought to be
able to get 15-28 defect-free, i860-sized microprocessor dice per
wafer.  Furthermore, we could design a bigger chip having 50% more area
(15mm x 15mm) and still produce 3 to 9 defect-free microprocessor dice.


(mounting the soapbox)
	This is, of course, only useful to estimate whether or not a
	chip is manufacturable.  If the expected yield is *extremely* small
	(say, below 1 die/wafer), we'd have to be very worried.  But,
	with an expected 3-to-9 die, we'll get a relatively smooth flow
	of good chips from the fab.

	What yield is *NOT* good for, is estimating product cost.  It
	only measures die cost.  To that you must add test cost(s),
	burn-in cost, depreciation on the $100M fab, depreciation on
	the array of $5M testers, package cost, QA and Reliability
	screen costs, design cost, and so forth.  Particularly for
	microprocessors, die cost is a *negligible* fraction of
	selling price.
(dismount)


So we can conclude that (*if* the defect density numbers in EE TIMES
are correct) "reasonable" folks who want guaranteed steady flow of
die can build them at 15x15 millimeters, today, in 1989.
   

{Note: in the table above, percent yield was calculated using the
"Poisson" model, which is known to be rather pessimistic.  According
to this model, percent yield == exp( -1.0 * A * D ).  In practice it
is usually observed that yields are higher than the Poisson model
predicts.  There are more accurate, more complicated models available
but this one is the most well-known formula.}
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
	...!decwrl!mips!mark	(408) 991-0208