Article View: comp.lsi
Article #1241Wired-OR in VLSI
From: Dik Lee
Date: Sat, 01 Apr 1989 13:55
Date: Sat, 01 Apr 1989 13:55
20 lines
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1441 bytes
I like to find out what are the pros and cons of using wired logic (Wired-AND/OR) in vlsi design. Wired-logic can save a lot of logic gates, but I know it will also consume a larger amount of power, introduce more capacitance, need time to settle, etc. etc. It seems to me that it is not widely used in VLSI design. Is this true? I can't find any thorough discussion in the literature about wired logic in VLSI (I read an article on IEEE 893 FutureBus which uses wired logic, but the discussion is not for VLSI). I like to hear from people who have experience with wired-logic or know some references. I am interested in both nMOS and cMOS. - Dik Lee Dept. Computer and Information Science dlee@cis.ohio-state.edu The Ohio State University ..!osu-cis!cis.ohio-state.edu!dlee Columbus, OHIO 43210-1277 614-292-2568 -- Dept. Computer and Information Science dlee@tut.cis.ohio-state.edu The Ohio State University ..!osu-cis!cis.ohio-state.edu!dlee Columbus, OHIO 43210-1277 614-292-2568
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!dlee From: dlee@tut.cis.ohio-state.edu (Dik Lee) Newsgroups: comp.lsi,comp.lsi.cad,comp.arch Subject: Wired-OR in VLSI Message-ID: <41352@tut.cis.ohio-state.edu> Date: 1 Apr 89 13:55:09 GMT Reply-To: Dik Lee <dlee@cis.ohio-state.edu> Followup-To: comp.lsi Organization: The Ohio State University Dept of Computer & Information Science Lines: 20