🚀 go-pugleaf

When talking about defects one must specify what kind of defects :
Spot defects ? Global deformations (under/over etching) ? Crystal
dislocations ?  Process related ? etc, etc, etc.  If assuming that the
mentioned defects are spot defects, then what kind of spot defects :
missing material ? extra material ? in what layer ?  Furthermore,
defects have to be characterized according to : type, size, frequency
of occurrence. Thus, a defect size distribution is needed.  Modern
yield prediction does not only take an IC as a black box in which
defects are placed. In fact if one looks inside of the "black box"
there are many places where the defects are less likely to damage the
IC. For instance, empty regions, bonding pads, etc, etc, etc. Assume
that we are dealing with spot defects. Whether a fault can occur or
not, depends on the critical area of the related patterns. The
critical area is the area where the center of a defect must fall to
introduce a fault.  Primitive faults at the IC level are: bridges,
breaks, extra devices, and missing devices.  Suppose now that we have
a spot defect of size x. The layer sensitivity S(x) (defined as the
ratio of the total critical area to the total IC area) multiplied by
the probability of occurrence of the defect gives the probability of
failure of the layer. Semiconductor yield is the probability of
manufacturing devices without faults. A more realistic expresion for
modeling yield is:
  Y(x,u) = ( 1 + c * A * D(x,u) * p(x,u)) ^ (-1/c)
where:
 x      = size of the defect
 u      = defect type
 Y(x,u) = yield of the layer due to defects of size x and type u
 c      = spatial defect clustering parameter
 A      = Area of the IC
 D(x,u) = Average defect density
 p(x,u) = Probability of failure of the layer.  

The IC yield is obtained by multiplying the yield of the individual
layers.  Poisson statistics are not always suitable because it cannot
model the defect density variations within the wafer, and from wafer
to wafer.  Thus, yield prediction is a bit more complicated than what
it looks like.  It is a bit naive attempting to predict the IC yield
just by knowing its area.
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Jose Pineda.
Design Automation Section, Dept. of Electrical Engr.
Eindhoven University of Technology P.O. Box 513 5600 MB, Eindhoven The
Netherlands.

Tel (040)-473373
Email: jose@euteal.UUCP
       (mcvax!hp4nl!eutrc3!euteal!jose)
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