🚀 go-pugleaf

In article <3102@buengc.BU.EDU> marco@buengc.bu.edu (Marco Zelada) writes:
>In article <98KK02mD33RK01@amdahl.uts.amdahl.com> sdg@amdahl.uts.amdahl.com (Subrata Dasgupta) writes:
>>
>>Mixed mode simulation is definitely viable and has been tried in chip
>>design  at various organizations.  I don't see any reason why it would
>>be possible to apply mixed mode simulation to a board-level design and
>>not be feasible for chip design. Speaking from my own experience at
>>Duke University, we simulate VLSI chips using Leonardo (a mixed-mode
>>simulator). It is possible to do functional/behavioral, gate-level,
>>and circuit-level simulation using Leonardo.
>
>	Where could one get the Leonardo simulator you mention here ?
>I would be very interested in trying it out on a project I am working
>on right now.
>
>	Thank you in advance.
>
>-- 

Leonardo is part of the OASIS package to be released by MCNC (Microlelectronics
Center of North Carolina) at the end of the summer.  The package includes
a mixed level simulator, a fault simulator, standard cell placement and route,
and a design description language.

The mixed level simulator (which I developed) is an off shoot of Chris Terman's
(MIT) RSIM.  Improved transistor switch level modeling is provided by Mark 
Horowitz and C.Y. Chu (Stanford).  The high level modelling language is an
enhanced C.  Simulation control may be done through C modules or from an
simple interpreter.  Mixed level extraction from Magic,  as well as gate 
level compiled simulation tools, are included.  I will provide more
details when we are ready for release.

A parallel version of the simulator running on BBN's Butterfly is in the
offing and will be available early next year (after I have finished my Ph.D.).