🚀 go-pugleaf

Gentlepersons

MOSIS is looking for a small number of volunteers from the University 
community to help test its net list to parts service prior to its 
introduction.

The way the test will be performed is as follows:
 
        (1) We will give you a design kit consisting of a
            library of std cells for Viewlogic's tools
            capable of being fabbed on MOSIS 1.6 micron
            processes.
        (2) You will capture your designs using Viewdraw.
        (3) You will send us designs in Viewlogic format.
        (4) We will place and route the design and send you back 
            a backannotated net list which takes into account
            capacitive loading due to wiring.            
        (5) If in redoing the timing simulation you find
            the place and route acceptable and if the chip
            fits into a Tiny Chip frame you will be able to
            ask us to fab the design for free.
	(6) The final day to submit a design for fabrication 
            will be 2/1/90.
        (7) Once you get chips, you will test them to determine
            whether the timing came out as predicted.

Send your name, your University affiliation, address, phone #, 
and e-mail address to "sllu@mosis.edu" or "mosis@mosis.edu".

We will choose five pioneers and get back to you with further information.

Even if you don't want to be a pioneer, feel free to respond. It would 
help us to know the number interested in using the service once
established.

If you do not have Viewlogic's tools, and if you are part of an educational
institution, you may qualify for a free loaner copy from USC/ISI's Integrated
Systems Laboratory. To find out you should contact Mr. Robert Parker or Mr. 
Jeff La Coss directly at (213)822-1511 x235 (jlacoss@venera.isi.edu). You 
can also ask us to ask them to contact you.


                    				Ms. MOSIS