🚀 go-pugleaf

In article <4025@mit-caf.MIT.EDU> shers@mit-caf.UUCP
(Alexander The Great Sherstinsky) writes:
>Vi   C
>----||----*-- Vo
>          |
>          /
>          \ R
>          /
>          \
>          |
>          GND
[...and asks how to bias this highpass so that Vo is about Supply/2...]

That's the AC model.  The DC model can look like:

          Vdd
          |
          /
          \ 2R
          /
          \
Vi   C    |
----||----*-- Vo  (Now Vo == Vdd/2)
          |
          /
          \ 2R
          /
          \
          |
          GND

Which is the answer.

There's a problem if you use turned-off enhancement FET's
for the 2R values, in that process control is very spotty
(and of limited economic value) in CMOS, and the pullup's
off-impedance may be an order of magnitude different from
the pulldown's, and good luck predicting which way.

Now, if you've got an _analog_ CMOS line on which to
produce these chips, or a process engineer who doesn't
mind a few days of knob-twiddling...

				--Blair
				  "Them's the breaks."