🚀 go-pugleaf

						April 11, 1997
Dear Colleague:

Please find Advance Programs of:
1997 Symposium on VLSI Technology, June 10-12, 1997
1997 Symposium on VLSI Circuits,   June 12-14, 1997,
which will be held in Kyoto, Japan.    
The deadline of advance registration is April 25.
More details, registration form, etc. can be obtained
from our home page.
	http://www.bcasj.or.jp/vlsi_sym/

We are looking forward to seeing you at the symposia.

Best Regards,

Hidetoshi Onodera
Kyoto University
(VLSI Symposia Publication)

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                     =================================
                     1997 SYMPOSIUM ON VLSI TECHNOLOGY
                     =================================

                             Rhiga Royal Hotel Kyoto
                                Kyoto, Japan
                             June 10 - 12, 1997

                                Sponsored by
                    The Japan Society of Applied Physics
                    and the IEEE Electron Device Society


                                   PROGRAM

                              Tuesday, June 10

 Session 1: Welcome and Plenary Session [Shunju]
 Chairpersons:S. Kawamura, Fujitsu
              T. Alvarez, Cypress

  8:30   1-1  Welcome and Opening Remarks
              Y. Hayashi, Sony
              B. Siu, Intel
  8:45   1-2  The 300mm Technology - Current Status and Future Prospect
              (Invited)
              H. Komiya, Selete, Japan
  9:25   1-3  Keeping Both Sides Winning: Wafer Fabrication Equipment
              Suppliers and Semiconductor Manufacturers in the Year 2000
              and Beyond (Invited)
              D. Maydan, Applied Materials, USA

                            (Break 10:05-10:25)

 Session 2: Highlights [Shunju]
 Chairpersons:T. Kunio, NEC
              C. Lage, Motorola

 10:25   2-1  Highly Manufacturable 1Gb SDRAM
              K.N. Kim, J.Y. Lee, K.H. Lee, B.H. Noh, S.W. Nam, Y.S. Park,
              Y.H. Kim, H.S. Kim, J.S. Kim, J.K. Park, K.P. Lee, K.Y. Lee,
              J.T. Moon, J.S. Choi, J.W. Par k and J.G. Lee
              Samsung Electronics, Korea
 10:50   2-2  A 4-um^{2} Full-CMOS SRAM Cell Technology for 0.2-um
              High-Performance Logic LSIs
              Y. Takao, Y. Sambonsugi*, K. Watanabe, H. Takatsuka, T.
              Karasawa, E. Kawamu ra, K. Hashimoto, H. Takagi, F. Inoue, H.
              Shimizu, T. Yamazaki, H. Goto, T. Sugii*, M. Miyajima, K.
              Watanabe and K. Aoyama
              Fujitsu and *Fujitsu Labs., Japan
 11:15   2-3  0.18um CMOS Technology for High-Performance, Low-Power, and
              RF Applications
              T.C. Holloway, G.A. Dixit, D.T. Grider, S.P. Ashburn, R.
              Aggarwal, A. Shih, X. Zhang, G. Misium, A.L. Esquivel, M.
              Jain, S. Madan, T. Breedijk, A. Singh , G. Thakar, G. Shinn,
              B. Riemenschneider, S. O'Brien, D. Frystak, J. Kittl, A.
              Amerasekera, S. Aur, P. Nicollian, D. Aldrich, B. Eklund, A.
              Appel, C. Bowles and T. Parrill
              Texas Instruments, USA
 11:40   2-4  Uniformity and Reliability of 1.5nm Direct Tunneling Gate
              Oxide MOSFETs
              H.S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E.
              Morifuji, T. Morimoto , Y. Katsumata and H. Iwai
              Toshiba, Japan

                            (Lunch 12:05-13:30)

 Session 3A: DRAMs I (Planarization Technology for DRAM Cell Formation)
 [Shunju I]
 Chairpersons:C.-G. Hwang, Samsung Electronics
              J. Abernathy, IBM Microelectronics

 13:30   3A-1 A Fully Printable, Self-Aligned and Planarized Stacked
              Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond
              Y. Kohyama, T. Ozaki, S. Yoshida, Y. Ishibashi, H. Nitta, S.
              Inoue, K. Naka mura, T. Aoyama, K. Imai and N. Hayasaka
              Toshiba, Japan
 13:55   3A-2 A Novel 1Gb Trench DRAM Cell with Raised Shallow Trench
              Isolation(RSTI)
              J. Alsmeier, K.H. Kelleher*, J. Beintner, W. Haensch, J.A.
              Mandelman*, P. H oh*, Y.L. Ninomiya*, S. Srinivasan and G.
              Bronner*
              Siemens Components and *IBM, USA
 14:20   3A-3 Fully Planarized Stacked Capacitor Cell with Deep and High
              Aspect Ratio Contact Hole for Giga-Bit DRAM
              K. Itabashi, S. Tsuboi, H. Nakamura, K. Hashimoto, W. Futoh,
              K. Fukuda, I. Hanyu, S. Asai, T. Chijimatsu, E. Kawamura, T.
              Yao, H. Takagi, Y. Ohta, T. K arasawa, H. Iio, M. Onoda, F.
              Inoue, H. Nomura, Y. Satoh, M. Higashimoto, M. Matsumiya, T.
              Miyabo, T. Ikeda, T. Yamazaki, M. Miyajima, K. Watanabe, S.
              Ka wamura and M. Taguchi
              Fujitsu, Japan
 14:45   3A-4 0.25um W-Polycide Dual Gate and Buried Metal on Diffusion
              Layer(BMD) Technology for DRAM-Embedded Logic Devices
              M. Tsukamoto, H. Kuroda and Y. Okamoto
              Sony, Japan

                            (Break 15:10-15:30)

 Session 3B: Interconnects I [Shunju II]
 Chairpersons:M. Kinugawa, Toshiba
              B. Havemann, Texas Instruments

 13:30   3B-1 Modeling of Chemical Mechanical Polishing Process for
              Three-Dimensional Simulation
              H. Takahashi, K. Tokunaga, T. Kasuga and T. Suzuki
              Sony, Japan
 13:55   3B-2 Dielectric Planarization Using Mn{2}O{3} Slurry
              S. Kishii, K. Nakamura and Y. Arimoto
              Fujitsu Labs., Japan
 14:20   3B-3 Scaling Inter-Poly Contacts for 0.25um and Below with WSi{x}
              Polishing
              A. Perera, T. Lii, S. Iyer, R. Bajaj, J. Pfiester*, C.
              Feng**, T. Dao**, D. O'Meara, B. Adetutu, K. McGuffin, R.
              Larson and M. Blackwell
              Motorola, *Hewlett-Packard and **Semiconductor Technology
              Lab., USA
 14:45   3B-4 Copper Integration in Self Aligned Dual Damascene
              Architecture
              Y. Morand, M. Lerme*, J. Palleau**, J. Torres**, F. Vinet*,
              O. Demolliens*, L. Ulmer*, Y. Gobil*, M. Fayolle*, F.
              Romagna** and R.L. Bihan
              SGS-Thomson Microelectronics, *LETI and **CNET-CNS, France

                            (Break 15:10-15:30)

 Session 4A: Advanced Manufacturing [Shunju I]
 Chairpersons:M. Inuishi, Mitsubishi Electric
              T. Seidel, Genus

 15:30   4A-1 A 5-Mask CMOS Technology
              H. Onishi, K. Imai, H. Nakamura, Y. Matsubara, Y. Yamada, T.
              Tamura, T. Sak ai and T. Horiuchi
              NEC, Japan
 15:55   4A-2 A Very High Performance, Epi-Free, and Manu facturable 3.3v
              0.35um BiCMOS Technology for Wireless Applications
              Y.F. Chyan, S. Chaudhry, Y. Ma, A.S. Chen, M.S. Carroll, W.J.
              Nagy, J. Bece rro, J.L. Lee, M.P. Iannuzzi and K.H. Lee
              Bell Labs., Lucent Technologies, USA
 16:20   4A-3 A Novel Environmentally-Friendly Corrosion-Free
              Post-Stripping Rinsing Procedure after Solvent Strip
              R. Vos, A. Rotondaro*, P.W. Mertens, M. Meuris and M. Heyns
              IMEC, Belgium and *Texas Instruments, USA

                           (Dinner 19:00 - 21:00)

 Session 4B: Modeling and Characterization [Shunju II]
 Chairpersons:T. Shibata, Tohoku Univ.
              W. Lynch, Semiconductor Research

 15:30   4B-1 New Insight on Electromigration Failure Mechanism and Its
              Impact on Design Guidelines
              D. Jawarani, M. Gall, R. Hernandez, C. Capasso and H.
              Kawasaki
              Motorola, USA
 15:55   4B-2 Physical Model for Contact Degradation at High Current
              Densities
              A. Neugroschel and C.-T. Sah
              Univ. of Florida, USA
 16:20   4B-3 Modeling and Characterization of Si/SiO2 Interface Roughness
              H.-C. Lin, E.C. Kan, T. Yamanaka* and C.R. Helms
              Stanford Univ., USA and *Hitachi, Japan

                           (Dinner 19:00 - 21:00)

                             Wednesday, June 11

 Session 5A: Gate Oxide Engineering [Shunju I]
 Chairpersons:M. Ohkura, Hitachi
              G. Declerck, IMEC

  8:30   5A-1 An Advanced 2.5nm Oxidized Nitride Gate Dielectric for Highly
              Reliable 0.25um MOSFETs
              T. Yamamoto, T. Ogura, Y. Saito, K. Uwasawa, T. Tatsumi and
              T. Mogami
              NEC, Japan
  8:55   5A-2 A 0.18um CMOS Process Using Nitrogen Profile-Engineered Gate
              Dielectrics
              D.T. Grider, S.V. Hattangady, R. Kraft, P.E. Nicollian, J.
              Kuehne, G. Brown , S. Aur, R.H. Eklund, M.F. Pas, W.R. Hunter
              and M. Douglas
              Texas Instruments, USA
  9:20   5A-3 A Novel Low-Temperature Gate Oxynitride for CMOS Technologies
              C. Diaz, M. Cox, W. Greene, F. Perlaki, E. Carr, I. Manna, A.
              Bayoumi, M. Cao, N. Shamma, M. Tavassoli, C. Chi, N. Farrar,
              D. Lefforge, Y. Chang, B. L angley and P. Marcoux
              Hewlett-Packard, USA
  9:45   5A-4 Ultra-Thin Silicon Nitride Gate Dielectric for
              Deep-Sub-Micron CMOS Devices
              M. Khare, X. Guo, X.W. Wang, T.P. Ma, G.J. Cui*, T.
              Tamagawa*, B.L. Halpern * and J.J. Schmitt*
              Yale Univ. and *Jet Process, USA

                            (Break 10:10-10:30)

 Session 5B: Interconnects II [Shunju II]
 Chairpersons:J. Ida, Oki Electric
              M. Bohr, Intel

  8:30   5B-1 Interconnect Scaling Scenario Using a Chip Level Interconnect
              Model
              K. Yamashita and S. Odanaka
              Matsushita Electric, Japan
  8:55   5B-2 A Simple Sub-0.3um CMOS Technology with Five-Level
              Interconnect Using Al-Plug and HSQ of Low-k for High
              Performance Processor
              K. Yoshiyama, K. Okada, M. Igarashi, K. Yamada, S. Shimizu,
              Y. Takata, A. O saki, K. Higashitani and S. Asai
              Mitsubishi Electric, Japan
  9:20   5B-3 A Novel Copper Reflow Process Using Dual Wetting Layers
              S. Hirao, M. Satake, H. Kamada, M. Sekiguchi, T. Tamaki and
              S. Mayumi
              Matsushita Electric, Japan
  9:45   5B-4 Ultra-Low Resistance Direct Contact Cu via Technology Using
              In-Situ Chemical Vapor Cleaning
              Y. Tsuchiya, K. Ueno, V.M. Donnelly*, T. Kikkawa, Y. Hayashi,
              A. Kobayashi** and A. Sekiguchi**
              NEC, Japan, *Bell Labs., Lucent Technologies, USA and
              **Anelva, Japan

                            (Break 10:10-10:30)

 Session 6A: Flash Memory I [Shunju I]
 Chairpersons:J. Kudo, Sharp
              G. De Santi, SGS-Thomson Microelectronics

 10:30   6A-1 A Novel CMOS Compatible Stacked Floating Gate Device Using
              TiN as a Control Gate
              K.J. O'Connor, W.M. Mansfield, J.D. Bude, M. Cerullo, F.
              Klemens, A. Kornbl it, M. Mastrapasqua, G.R. Weber and W.W.
              Tai
              Bell Labs., Lucent Technologies, USA
 10:55   6A-2 A Novel Flash Memory Device with Split Gate Source Side
              Injection and ONO Charge Storage Stack(SPIN)
              W.-M. Chen, C. Swift, D. Roberts, K. Forbes, J. Higman, B.
              Maiti, W. Paulso n and K.-T. Chang
              Motorola, USA
 11:20   6A-3 Fast Parallel Programming of Multi-Level NAND Flash Memory
              Cells Using the Booster-Line Technology
              H.S. Kim, J.D. Choi, J. Kim, W.C. Shin, D.J. Kim, K.M. Mang
              and S.T. Ahn
              Samsung Electronics, Korea
 11:45   6A-4 A New Flash Architecture with a 5.8lamda^2 Scalable AMG Flash
              Cell
              A. Roy, R. Kazerounian, R. Irani, V. Prabhakar, S. Nguyen, Y.
              Slezak, C. Tr inh, P. Kauk, M. Agarwal, B. Eitan, R.
              Annunziata*, E. Camerlenghi*, A. Camp isi*, P. Cappelletti*,
              E. Colabella*, G. Crisenza*, M. Dallabora*, G. Fontan a*, L.
              Pividori* and M. Tosi*
              WSI, USA and *SGS-Thomson Microelectronics, Italy

                            (Lunch 12:10-13:30)

 Session 6B: Novel MOSFET Structures [Shunju II]
 Chairpersons:N. Ouchi, Sony
              R. Liu, Lucent Technology Bell Labs.

 10:30   6B-1 Dual Threshold Voltages and Substrate Bias: Keys to High
              Performance, Low Power, 0.1um Logic Designs
              S. Thompson, I .Young, J. Greason and M. Bohr
              Intel, USA
 10:55   6B-2 Advanced Gate-Stack Architecture for Low-Voltage
              Dual-Workfunction CMOS Technologies with Shallow Trench
              Isolation
              U. Schwalke, M. Kerber, K. Koller, B. Ludwig and A. Seidl
              Siemens, Germany
 11:20   6B-3 A Mesh-Arrayed MOSFET(MA-MOS) for High-Frequency Analog
              Applications
              H. Shimomura, A. Matsuzawa, H. Kimura, G. Hayashi, T. Hirai
              and A. Kanda
              Matsushita Electric, Japan
 11:45   6B-4 A 5.5um CMOS Image Sensor Cell Utilizing a Buried Reset
              Channel
              K. Mabuchi, M. Sasaki and R. Miyagawa
              Toshiba, Japan

                            (Lunch 12:10-13:30)

 Session 7A: Low k Dielectrics [Shunju I]
 Chairpersons:J. Ida, Oki Electric
              S. Somekh, Applied Materials

 13:30   7A-1 Integration of Ultra-Low-k Xerogel Gapfill Dielectric for
              High Performance Sub-0.18um Interconnects
              R.S. List, C. Jin, S.W. Russell, S. Yamanaka, L. Olsen, L.
              Le, L.M. Ting an d R.H. Havemann
              Texas Instruments, USA
 13:55   7A-2 0.6um Pitch Highly Reliable Multilevel Interconnection Using
              Hydrogen Silicate Based Inorganic SOG for Sub-Quarter Micron
              CMOS Technology
              N. Oda, T. Usami, K. Kishimoto, A. Matsumoto, K. Mikagi, K.
              Kikuta, H. Gomi and I. Sakai
              NEC, Japan
 14:20   7A-3 Integration of Thermally Stable, Low-k AF4 Polymer for 0.18um
              Interconnects and Beyond
              A.R.K. Ralston, J.F. Gaynor, A. Singh, L.V. Le, R.H.
              Havemann, M.A. Plano*, T.J. Cleary*, J.C. Wing* and J. Kelly*
              Texas Instruments and *Novellus Systems, USA
 14:45   7A-4 Implication and Solutions for Joule Heating in High
              Performance Interconnects Incorporating Low-k Dielectrics
              W.-Y. Shih, M.-C. Chang, R.H. Havemann and J. Levine
              Texas Instruments, USA

                            (Break 15:10-15:30)

 Session 7B: Channel and Source/Drain Engineering [Shunju II]
 Chairpersons:S. Odanaka, Matsushita Electric
              Y. Taur, IBM

 13:30   7B-1 Transient-Enhanced Diffusion of Indium and Its Effects on
              Electrical Characteristics of Deep Sub-Micron nMOSFETs
              M. Cao, P. Griffin*, P.V. Voorde, C. Diaz and W. Greene
              Hewlett-Packard Labs. and *Stanford Univ., USA
 13:55   7B-2 Channel Profile Control Based on Transient-Enhanced-Diffusion
              Suppression by RTA for 0.18um Single Gate CMOS
              A. Furukawa, A. Teramoto, S. Shimizu, Y. Abe and Y. Tokuda
              Mitsubishi Electric, Japan
 14:20   7B-3 Boron Implanted Shallow Junction Formation by
              High-Temperature/Short-Time/High-Ramping-Rate(400 C/sec) RTA
              S. Shishiguchi, A. Mineji, T. Hayashi and S. Saito
              NEC, Japan
 14:45   7B-4 Manufacturable Shallow-Junction Processes to Overcome Defect
              Formation and Dopant Reactions for Sub-0.18um CMOS
              Technologies
              C.T. Liu, F.H. Baumann, H.H. Vuong, C.S. Pai, D.J. Eaglesham,
              R. Liu, C.P. Chang, K.P. Cheung, J.I. Colonell, W.Y.C. Lai
              and S.J. Hillenius
              Bell Labs., Lucent Technologies, USA

                            (Break 15:10-15:30)

 Session 8A: SOI Technology [Shunju I]
 Chairpersons:S. Konaka, NTT
              J. Woo, UCLA

 15:30   8A-1 A Highly Reliable 0.35um Field-Shield Body-Tied SOI Gate
              Array for Substrate-Bias-Effect Free Operation
              S. Maeda, Y. Yamaguchi, I.-J. Kim, T. Iwamatsu, T. Ipposhi,
              S. Miyamoto, Y. Hirano, K. Ueda, K. Nii, K. Mashiko, S.
              Maegawa, Y. Inoue and T. Nishimura
              Mitsubishi Electric, Japan
 15:55   8A-2 An Advanced Ge Pre-Amorphization Salicide Technology for
              Sub-Quarter-Micrometer SOI CMOS Devices
              T.C. Hsiao, P. Liu and J.C.S. Woo
              UCLA, USA
 16:20   8A-3 A Novel Technique for 3-D Integration: Ge-Seeded Laterally
              Crystallized TFTs
              V. Subramanian and K.C. Saraswat
              Stanford Univ., USA
 16:45   8A-4 Correlation between Low-Frequency Noise Overshoot in SOI
              MOSFETs and Frequency Dependence of Floating Body Effect
              Y.-C. Tseng, W.M. Huang*, J.A. Babcock**, J.M. Ford* and
              J.C.S. Woo
              UCLA, *Motorola and **Arizona State Univ., USA

 Session 8B: Gate Engineering MOSFETs [Shunju II]
 Chairpersons:M. Ohkura, Hitachi
              G. Bomchil, France Telecom

 15:30   8B-1 0.25um CoSi2 Salicide CMOS Technology Thermally Stable up to
              1,000 C with High TDDB Reliability
              T. Ohguro, S. Nakamura, E. Morifuji, T. Yoshitomi, T.
              Morimoto, H. Harakawa , H.S. Momose, Y. Katsumata and H. Iwai
              Toshiba, Japan
 15:55   8B-2 Salicides for 0.10um Gate Lengths: A Comparative Study of
              One-Step RTP Ti with Mo Doping, Ti with Pre-Amorphization and
              Co Processes
              J.A. Kittl, Q.-Z. Hong, C.-P. Chao, I.-C. Chen, N. Yu, S.
              O'Brien and M. Hanratty
              Texas Instruments, USA
 16:20   8B-3 Gate Engineering for Performance and Reliability in
              Deep-Submicron CMOS Technology
              B. Yu, D.-H. Ju*, N. Kepler*, T.-J. King and C. Hu
              UC Berkeley and *Advanced Micro Devices, USA
 16:45   8B-4 Gate Electrode Engineering by Control of Grain Growth for
              High Performance and High Reliable 0.18um Dual Gate CMOS
              S. Shimizu, T. Kuroi, H. Sayama, A. Furukawa, Y. Nishida, Y.
              Inoue, M. Inuishi and T. Nishimura
              Mitsubishi Electric, Japan

20:00 Rump Sessions:

 Organizers:M. Inuishi, Mitsubishi Electric
            B. Havemann, Texas Instruments

R-1 Merged Logic and DRAM
    (Technology and Circuits Joint Session)
    Moderators:              M. Yamawaki, Mitsubishi Electric
                             S. Stiffler, IBM
                             C. Kim, Samsung Electronics
                             D. Scott, Texas Instruments
    Do merged logic and DRAM integrated circuits have a viable future ? The
    issues involved relate to performance, process complexity, testing,
    manufacturing and even the culture of the technical community. We will
    discuss the types of application that may be suitable for merged DRAM
    and logic integrated circuits. Further we will pose the challenge of
    how these products can be tested within the constraints already imposed
    by pure logic and DRAM implementations.

R-2 The Interconnect Crisis
    Moderators:              Y. Arimoto, Fujitsu Labs.
                             B. Zetterlund, Digital Equipment
    Can VLSI sustain the traditional rate of improvement in price and
    performance without integrating copper and low-K dielectrics into
    manufacturable processes? Which products will be the first to adopt
    these new materials? Will major insertion of these materials occur in
    the 0.25um, 0.18um, or subsequent generations? Several methods for
    copper line formation and many low-K dielectric constant materials are
    under study - which show the most promise? Will these materials be used
    throughout the interconnect or mixed and matched with conventional
    materials? How can the advantages in R, C, EMR realizable with these
    materials best be utilized in memories, ASICS, and microprocessors ?
    Will the lower thermal conductivity of low-K dielectrics be a
    significant problem? Will the way in which fine and coarse pitch layers
    are used for signals, clocks, and power distribution change because of
    these new materials?

R-3 Ferroelectric Memory
    Moderators:              T. Kunio, NEC
                             M. Anthony, Texas Instruments
    Ferroelectric memories utilize an electrically polarizable material
    such as Pb(Zr,Ti)O_{3} or SrBi_{2}Ta_{2}O_{9} to store information in a
    non-volatile fashion. Recent improvements in the understanding of these
    materials and associated electrodes allow the possibility of high
    density memories with multiple (>1E10) read/write cycles and low
    voltage (few volts) switching. This discussion section will address two
    major issues associated with these materials.
    1)What are the appropriate products for a ferroelectric memory, and how
    do they compare with existing strategies (including both stand-alone
    and embedded applications)?
    2)What are the crucial materials/integration issues associated with
    implementation and how can these issues be addressed?
    Typical examples might include the effect of etch damage or hydrogen
    based anneals on the ferroelectric properties. Approximately one hour
    will be devoted to each topic.

R-4 Surface Control and Thin Gate Oxides
    Moderators:              M. Hirose, Hiroshima Univ.
                             M. Heyns, IMEC
    The electrical properties of thermally grown ultra-thin SiO_{2} layers
    on Si are a critical issue for the characteristics of deep submicron
    CMOS devices. For these ultra-thin sub-3-nm gate oxides, direct quantum
    mechanical tunneling of electrons between the poly-Si gate and the
    Si-substrate becomes very important. Little is known about the
    ultra-thin oxide reliability in this case. Many issues are also still
    open on the surface preparation/cleaning technology needed to produce
    these layers with sufficiently low defect density. A perfect surface
    control on an atomic scale will be needed to grow layers that meet the
    stringent targets set by the SIA-roadmap. Various routes have been
    explored to obtain 'improved' gate oxides, including nitrided and
    N_{2}O-grown layers. There is no doubt that the physical limits of
    SiO_{2} are almost reached and a new dielectric gate material will be
    needed in the future. At the present time there is no
    material-of-choice to replace SiO_{2}. The issue of surface control and
    thin dielectrics will therefore become a major roadblock in the
    development of future generation technologies

                              Thursday, June 12

 Session 9A: Flash Memory II [Shunju I]
 Chairpersons:E. Suzuki, Electrotechnical Lab.
              J. Winnerl, Siemens

 8:30   9A-1  A New Oxide Damage Characterization Technique for Evaluating
              Hot Carrier Reliability of Flash Memory Cell after P/E Cycles
              S.S. Chung, C.M. Yih, S.M. Cheng and M.S. Liang*
              National Chiao Tung Univ. and *TSMC, Taiwan
 8:55   9A-2  A Novel SONOS Structure for Nonvolatile Memories with
              Improved Data Retention
              H. Reisinger, M. Franosche, B. Hasler and T. Bohm
              Siemens, Germany
 9:20   9A-3  A Novel nm-Grain Poly-Si Gate Structure for Reduction of Cell
              to Cell Write/Erase Tunnel Current Deviation in High Speed
              Quarter Micron FLASH Memories
              J. Yugami and T. Mine
              Hitachi, Japan
 9:45   9A-4  A Novel High K Inter-Poly Dielectric(IPD), Al_{2}O_{3} for
              Low Voltage/High Speed Flash Memories: Erasing in Msecs at 3.
              3V
              W.-H. Lee, J.T. Clemens, R.C. Keller and L. Manchanda
              Bell Labs., Lucent Technologies, USA

                            (Break 10:10-10:30)

 Session 9B: Shallow Trench Isolation [Shunju II]
 Chairpersons:M. Kinugawa, Toshiba
              C. van der Poel, Philips

 8:30   9B-1  Impact of Trench Sidewall Interface Trap in Shallow Trench
              Isolation on Junction Leakage Current Characteristics for
              Sub-0.25um CMOS Devices
              S. Inaba, M. Takahashi, Y. Okayama, A. Yagishita, F. Matsuoka
              and H. Ishiuchi
              Toshiba, Japan
 8:55   9B-2  A Very Simple Trench Isolation(VSTI) Technology with
              Chemo-Mechanically Polished(CMP) Substrate Si
              T. Park, H.S. Lee, Y.G. Shin, C.G. Hong, H.K. Kang, Y.B. Koh
              and M.Y. Lee
              Samsung Electronics, Korea
 9:20   9B-3  Mechanical Stress Induced MOSFET Punch-through and Process
              Optimization for Deep Submicron TEOS-O_{3} Filled STI Device
              K. Ishimaru, F. Matsuoka, M. Takahashi, M. Nishigohri, Y.
              Okayama, Y. Unno* , M. Yabuki, K. Umezawa, N. Tsuchiya, O.
              Fujii and M. Kinugawa
              Toshiba and *Toshiba Microelectronics, Japan
 9:45   9B-4  A Robust 0.15um CMOS Technology with CoSi_{2} Salicide and
              Shallow Trench Isolation
              H. Kawaguchi, H. Abiko, K. Inoue, Y. Saito, T. Yamamoto, Y.
              Hayashi, S. Mas uoka, A. Ono, T. Tamura, K. Tokunaga, Y.
              Yamada, K. Yoshida and I. Sakai
              NEC, Japan

                            (Break 10:10-10:30)

 Session 10A: Micro-structures [Shunju I]
 Chairpersons:T. M. Liu, TSMC
              R. De Keersmaecker, IMEC

 10:30 10A-1  Deep-UV Lithographic Approaches for 1Gb DRAM
              A. Wong, T. Farrell, R. Ferguson, G. Lu*, S. Mansfield, A.
              Molless, M. Neis ser, R. Nunes, D. Samuels and A. Thomas
              IBM and *Siemens, USA
 10:55 10A-2  Fabrication of 100nm pMOSFETs with Hybrid AFM/STM Lithography
              H.T. Soh, K. Wilder, A. Atalar and C.F. Quate
              Stanford Univ., USA
 11:20 10A-3  Fabrication of 0.06um Poly-Si Gate Using DUV Lithography with
              a Designed Si_{x}O_{y}N_{z} Film as an ARC and Hardmask
              W.W. Lee, Q. He, M. Hanratty, D. Rogers, A. Chatterjee, R.
              Kraft and R.A. Chapman
              Texas Instruments, USA
 11:45 10A-4  Technology and Power-Speed Trade-Offs in Quantum-Dot and
              Nano-Crystal Memory Devices
              S. Tiwari, J.J. Welser and F. Rana
              IBM, USA

                            (Lunch 12:10-13:30)

 Session 10B: Advanced Dielectrics [Shunju II]
 Chairpersons:J. Kudo, Sharp
              D. Kyser, Advanced Micro Devices

 10:30 10B-1  Ultra-Thin Ta_{2}O_{5}/SiO_{2} Gate Insulator with TiN Gate
              Technology for 0.1um MOSFETs
              Y. Momiyama, H. Minakata and T. Sugii
              Fujitsu Labs., Japan
 10:55 10B-2  Low-Damage ECR-Plasma-Etching Technique for
              SrBi_{2}Ta_{2}O_{9} (SBT) Capacitor in FeRAM Devices
              Y. Maejima, S. Saitoh and Y. Hayashi
              NEC, Japan
 11:20 10B-3  A 1T/1C Ferroelectric RAM Using a Double-Level Metal Process
              for Highly Scalable Nonvolatile Memory
              D.-J. Jung, N.-S. Kang, S.-Y. Lee, B.-J. Koo, J.-W. Lee,
              J.-H. Park, Y.-S. Chun, M.-H. Lee, B.-G. Jeon, S.-I. Lee,
              T.-E. Shim and C.-G. Hwang
              Samsung Electronics, Korea
 11:45 10B-4  Computationally Efficient Ferroelectric Capacitor Model for
              Circuit Simulation
              B. Jiang, P. Zurcher*, R.E. Jones*, S.J. Gillespie* and J.C.
              Lee
              Univ. of Texas at Austin and *Motorola, USA

                            (Lunch 12:10-13:30)

 Session 11: Thin Oxide Modeling [Shunju I]
 Chairpersons:E. Suzuki, Electrotechnical Lab.
              B. Zetterlund, Digital Equipment

 13:30  11-1  A New Dielectric Breakdown Mechanism in Silicon Dioxides
              K. Okada
              Matsushita Electric, Japan
 13:55  11-2  Energy Funnels -A New Oxide Breakdown Model
              K.P. Cheung, J. Colonell, C.P. Chang, W.Y.C. Lai, C.T. Liu,
              R. Liu and C.S. Pai
              Bell Labs., Lucent Technologies, USA
 14:20  11-3  Charging and Intrinsic-Leakage Current Peaks in Thin
              Silicon-Dioxide Films
              R. Yamada, J. Yugami and M. Ohkura
              Hitachi, Japan
 14:45  11-4  Modeling and Characterization of n^{+}- and p^{+}-
              Polysilicon-Gated Ultra Thin Oxides(21-26A)
              S.-H. Lo, D.A. Buchanan, Y. Taur, L.-K. Han and E. Wu
              IBM, USA

                            (Break 15:10-15:30)

 Session 12: DRAMs II [Shunju I]
 Chairpersons:M. Inuishi, Mitsubishi Electric
              C. Dennison, Micron Technology

 15:30  12-1  Cylindrical Full Metal Capacitor Technology for High-Speed
              Gigabit DRAMs
              J.M. Drynan, K. Nakajima, T. Akimoto, K. Saito, M. Suzuki, S.
              Kamiyama and Y. Takaishi
              NEC, Japan
 15:55  12-2  The Simplest Stacked BST Capacitor for the Future DRAMs Using
              a Novel Low Temperature Growth Enhanced Crystallization
              S. Takehiro, S. Yamauchi, M. Yoshimaru and H. Onoda
              Oki Electric, Japan
 16:20  12-3  A Novel Merged Gain Cell for Logic Compatible High Density
              DRAMs
              M. Mukai, Y. Hayashi and Y. Komatsu
              Sony, Japan
 16:45  12-4  Suppression of Bit-Line-Induced Disturbance in SOI DRAM/SRAM
              Cells by Bipolar Embedded Source Structure(BESS)
              M. Horiuchi, T. Sakata and S. Kimura
              Hitachi, Japan
 17:10Closing

============================================================================

                      ===============================
                      1997 SYMPOSIUM ON VLSI CIRCUITS
                      ===============================

                           Rhiga Royal Hotel Kyoto
                                Kyoto, Japan
                             June 12 - 14, 1997

                                Sponsored by
                    The Japan Society of Applied Physics
                 and the IEEE Solid-State Circuits Council
             In Cooperation with the Institute of Electronics,
                  Information and Communication Engineers


                                   PROGRAM

                              Thursday, June 12

 Session 1: Welcome and Plenary Session [Suzaku I, II]
 Chairpersons:T. Sakurai, Univ. of Tokyo
              W. Bidermann, Chromatic Research

  8:30    1-1 Welcome and Opening Remarks
              T. Masuhara, Hitachi
              I . Young, Intel
  8:45    1-2 Evolution of DVD by Advanced Semiconductor Technology
              (Invited)
              H. Nakatsuka, Toshiba, Japan
  9:30    1-3 The 50th Anniversary of the Transistor-Historical Overview
              and Future Directions (Invited)
              J. Moll, Hewlett-Packard, USA

                            (Break 10:15-10:35)

 Session 2: High-Speed Microprocessor Design [Suzaku I, II]
 Chairpersons:M. Yamashina, NEC
              I. Young, Intel

  10:35   2-1 The Design of 300MIPS Microprocessor with a Full Associative
              TLB for Hand-Held PC OS
              K. Ishibashi, H. Higuchi, Y. Shimbo*, F. Arakawa, O. Nishii,
              N. Nakagawa, H . Maejima, K. Osada, K. Norisue*, R. Satomura,
              Aoki, Y. Shimazaki, K. Tanaka , T. Hattori, K. Shiozawa, K.
              Kudo, K. Uchiyama, S. Narita, J. Nishimoto, T. Nagano, S.
              Ikeda, K. Kuroda, T. Takeda and N. Hashimoto
              Hitachi and *Hitachi ULSI Eng., Japan
  11:00   2-2 Issue Logic for a 600MHz Out-of-Order Execution
              Microprocessor
              J.A. Farrell and T.C. Fischer
              Digital Equipment, USA
  11:25   2-3 A CMOS Temperature Sensor for Power PC{TM} RISC
              Microprocessors
              H. Sanchez, R. Philip, J. Alvarez and G. Gerosa
              Motorola, USA
  11:50   2-4 A 4.5 Megabit, 560MHz, 4.5GByte/s High Bandwidth SRAM
              J. Greason, D. Buehler, J. Kolousek, Y.-G. Ng, K. Sarkez, P.
              Shay and A. Wa izman
              Intel, USA

                            (Lunch 12:15-13:45)

 Session 3: High Speed and High Precision A/D Converters [Suzaku I]
 Chairpersons:M. Katakura, Sony
              L. DeVito, Analog Devices

  13:45   3-1 A Delta-Sigma Pulse Width Modulator with Pulse Dithering
              R.S. Lewison and D.J. Allstot*
              Oregon State Univ. and *Hewlett-Packard, USA
  14:10   3-2 1.2V, 16-bit Audio A/D Converter with Suppressed Latch Error
              Noise
              Y. Matsuya and J. Terada
              NTT, Japan
  14:35   3-3 CMOS Charge-Transfer Preamplifier for Offset-Fluctuation
              Cancellation in Low-Power, High-Accuracy Comparators
              K. Kotani, T. Shibata and T. Ohmi
              Tohoku Univ., Japan
  15:00   3-4 An 8-GSa/s 8-Bit ADC System
              K. Poulton, K.L. Knudsen, J. Kerley, J. Kang, J. Tani, E.
              Cornish and M. Va nGrouw
              Hewlett-Packard, USA

                            (Break 15:25-15:45)

 Session 4: Emerging Digital Circuits [Suzaku II]
 Chairpersons:M. Fujishima, Univ. of Tokyo
              M. Afghahi, Intel

  13:45   4-1 Self-Powered Low Power Signal Processing
              R. Amirtharajah and A. Chandrakasan
              MIT, USA
  14:10   4-2 A 32x32-Bit Adiabatic Register File with Supply Clock
              Generator
              Y. Moon and D.-K. Jeong
              Seoul National Univ., Korea
  14:35   4-3 Active Body-Bias SOI-CMOS Driver Circuits
              Y. Wada, K. Ueda, T. Hirota, Y. Hirano, K. Mashiko and H.
              Hamano
              Mitsubishi Electric, Japan
  15:00   4-4 Pass-Transistor/CMOS Collaborated Logic: T he Best of Both
              Worlds
              S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata*, K.
              Rikino** and K. Seki
              Hitachi, *Hitachi ULSI Eng. and **Hitachi Device Eng., Japan

                            (Break 15:25-15:45)

 Session 5: Interface and Simulation Technique [Suzaku I]
 Chairpersons:H. Onodera, Kyoto Univ.
              P. Gray, UC Berkeley

  15:45   5-1 High Speed Low EMI Digital Video Interface with Cable
              Deskewing and Transition Minimization Coding
              K. Lee, S. Kim, D.-K. Jeong, V.D. Costa*, G. Kim* and B. Kim*
              Seoul National Univ., Korea and *Silicon Image, USA
  16:10   5-2 A Multi-Mode Digital Detector Readout for Solid-State Medical
              Imaging Detectors
              C.D. Boles, B.E. Boser, B.H. Hasegawa* and J.A. Heanue
              UC Berkeley and *UC San Francisco, USA
  16:35   5-3 A Macroscopic Substrate Noise Model for Full Chip
              Mixed-Signal Design Verification
              M. Nagata and A. Iwata
              Hiroshima Univ., Japan

 Session 6: High Speed Circuits [Suzaku II]
 Chairpersons:K. Ueda, Matsushita Electric
              H. Kalter, IBM

  15:45   6-1 High Speed Adder Circuit Using Dummy Carry Method
              J. Mori, Y. Kondo and N. Ikumi
              Toshiba, Japan
  16:10   6-2 A 500MHz 32-Word x 64-Bit 8-Port Self-Resetting CMOS Register
              File and Associated Dynamic-to-Static Latch
              W.H. Henkels, W. Hwang and R.V. Joshi
              IBM, USA
  16:35   6-3 Precharged Cache Hit Logic with Flexible Timing Control
              W. Reohr, J. Navarro, Y.H. Chan, Y. Chan, M. Mayo, B. Curran,
              B. Krumm, A. Pelella, P.F. Lu, U. Bakhru, S. Kowalczyk, J.
              Rawlins, S. Carey and P. Wu
              IBM, USA

20:00 Rump Session:

R-1  1GHz and Beyond - PLL and Clock Distribution
     Moderators:             N. Ishihara, NTT
                              M. Afghahi, Intel

    The speed of the LSIs used in RISC processors and for synchronous
    memory has reached as high as several hundred MHz using on-chip PLLs
    and precise clock distribution technology. In the near future, will it
    be possible to exceed 1 GHz easily? Will this require break through
    technologies or not? Panelists will discuss solutions to the problems
    associated with the PLL structure, clock distribution techniques, power
    saving techniques, design tools, LSI chip mounting and testing, and try
    to predict when the speed will exceed 1GHz and what will limit the
    speed in the future.

R-2 Competing Architectures and Cell Technologies for High Performance
    DRAMs
    Moderators:             M. Taguchi, Fujitsu
                            W. K. Loh, Texas Instruments

    Innovative technologies for reducing the Processor to Main Memory
    bandwidth bottleneck such as Double Data Rate (DDR) SDRAM and
    high-speed packet based architectures like RAMBUS or SynchLink will
    propel the industry to several Gigabyte/second data transfer rates.
    However, the core DRAM array remains fundamentally slow despite
    multi-bank segmentation methods. Several aspects such as reduction of
    internal operating voltage or cosmic ray events impose limits on
    minimum stored charge to sense margins. Internally ``boosted'' level
    continue to place constraints on gate oxide thickness due to maximum
    allowable e-fields. Alternative cell technologies like ferroelectric
    and high-K dielectric storage cells are in or near production.
    Multi-level storage schemes or NAND-type cells are also proposed and
    are under investigation. Stacked capacitor technology seems to be
    dominant but trench technology now again draws attention for RAM and
    Logic application capability. This panel will discuss the impact of
    these technologies on future DRAM devices for tomorrow's computers
    using today's innovations.

R-3 Will the Single-Chip RF Transceiver Dominate in the Range of 1 to 2GHz?
    Moderators:             T. Tsukahara, NTT
                            A. A. Abidi, UC Los Angeles

    Is it worth striving for very high levels of integration, in terms of
    the final cost and performance? Integrated transceiver chips are large,
    with many inductors and large capacitors integrated with the active
    devices. Since small level RF and large level baseband signals are
    processed on the same chip, are crosstalk issues in a Si substrate
    still serious? Will the evolution of RF transceivers architectures to
    direct-conversion or quasi-IF configurations give true single-chip RF
    transceivers which have only RF and baseband ports, and power supplies?

Joint Rump Session with Technology:  Merged Logic and DRAM
    *This session will be held at the technology rump session on June 11
    Circuit Moderators/Organizers:
                            C. Kim, Samsung Electronics
                            D. Scott, Texas Instruments
    Technology Moderators/Organizers:
                            M. Yamawaki, Mitsubishi Electric
                            S. Stiffler, IBM

    Do merged logic and DRAM integrated circuits have a viable future ? The
    issues involved relate to performance, process complexity, testing,
    manufacturing and even the culture of the technical community. We will
    discuss the types of application that may be suitable for merged DRAM
    and logic integrated circuits. Further we will pose the challenge of
    how these products can be tested within the constraints already imposed
    by pure logic and DRAM implementations.

                               Friday, June 13

 Session 7: Plenary Session II [Shunju I, II]
 Chairpersons: T. Sakurai, Univ. of Tokyo
               W. Bidermann, Chromatic Research

  8:30    7-1  Technology Innovations in Mobile Computers(Invited)
               K. Ishida, IBM Japan, Japan
  9:15    7-2  Designing High Speed Microprocessors(Invited)
               P. Gronowski, Digital Equipment, USA

                            (Break 10:00-10:20)

 Session 8: Merged DRAM and Logic [Shunju I, II]
 Chairpersons: C. Kim, Samsung
               W. K. Loh, Texas Instruments

  10:20   8-1  An Embedded DRAM-FPGA Chip with Instantaneous Logic
               Reconfiguration
               M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe and M.
               Yamashina
               NEC, Japan
  10:45   8-2  A Pixel-Parallel Image Processor Using Logic Pitch-Matched
               to Dynamic Memory
               J.C. Gealow and C.G. Sodini
               MIT, USA
  11:10   8-3  An Access-Sequence Control Scheme to Enhance Random Access
               Performance of Embedded DRAMs
               K. Ayukawa, T. Watanabe and S. Narita
               Hitachi, Japan

                            (Lunch 11:35-13:15)

 Session 9: Flash Memories [Shunju I]
 Chairpersons: K. Nakahara, Sharp
               C. Kuo, Motorola

  13:15   9-1  Floating-Well Charge Pump Circuits for Sub -2.0V Single
               Power Supply Flash Memories
               K.-H. Choi, J.-M. Park, J.-K. Kim, T.-S. Jung and K.-D. Suh
               Samsung Electronics, Korea
  13:40   9-2  Circuit Technologies for a Single-1.8V Flash Memory
               T. Tanzawa, T. Tanaka, K. Takeuchi and H. Nakamura
               Toshiba, Japan
  14:05   9-3  A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Saving
               40% Die Size Per Bit
               T. Tanaka, T. Tanzawa and K. Takeuchi
               Toshiba, Japan
  14:30   9-4  A Multi-Page Cell Architecture for High-Speed Programming
               Multi-Level NAND Flash Memories
               K. Takeuchi, T. Tanaka and T. Tanzawa
               Toshiba, Japan

                            (Break 14:55-15:15)

 Session 10: Data Communication Circuits [Shunju II]
 Chairpersons: N. Ishihara, NTT
               T. H. Meng, Stanford Univ.

  13:15  10-1  A 2.4-Gb/s CMOS Clock Recovering 1:8 Demultiplexer
               M. Soda, H. Tezuka, S. Shioiri, A. Tanabe, A. Furukawa, M.
               Togo, T. Tamura and K. Yoshida
               NEC, Japan
  13:40  10-2  A 0.6um CMOS 4Gb/s Transceiver with Data Recovery Using
               Oversampling
               C.-K.K. Yang, R. Farjad-Rad and M. Horowitz
               Stanford Univ., USA
  14:05  10-3  An 11.8-GHz 31-mW CMOS Frequency Divider
               M. Kurisu, M. Nishikawa, H. Asazawa, A. Tanabe, M. Togo and
               A.Furukawa
               NEC, Japan
  14:30  10-4  A Phase Interpolation Direct Digital Synthesizer with a
               Digitally Controlled Delay Generator
               H. Nosaka, T. Nakagawa and A. Yamagishi
               NTT, Japan

                            (Break 14:55-15:15)

 Session 11: SRAMs and Non-Volatile Memories [Shunju I]
 Chairpersons: K. Mashiko, Mitsubishi Electric
               M. Horowitz, Stanford Univ.

  15:15  11-1  A Charge Transfer Amplifier and an Encoded Bus Architecture
               for Low Power SRAM
               S. Kawashima, T. Mori, R. Sasagawa, M. Hamaminato, S.
               Wakayama, K Sukegawa* and I. Fukushi
               Fujitsu Labs. and *Fujitsu, Japan
  15:40  11-2  A Hierarchical Sensing Scheme(HSS) of High-Density and
               Low-Voltage Operation SRAMs
               Y. Haraguchi, T. Wada and Y. Arita
               Mitsubishi Electric, Japan
  16:05  11-3  Low Supply Voltage CMOS Charge Pumps
               J.-T. Wu and K.-L. Chang*
               National Chiao Tung Univ. and *Macronix International,
               Taiwan
  16:30  11-4  High-Density Chain Ferroelectric Random-Access Memory
               (CFRAM)
               D. Takashima, I. Kunishima, M. Noguchi and S. Takagi
               Toshiba, Japan

                            (Dinner 18:00-20:00)

 Session 12: RF Circuits [Shunju II]
 Chairpersons: Y. Sugimoto, Chuo Univ.
               G. Nasserbakht, Texas Instruments

  15:15  12-1  On-Chip Spiral Inductors with Patterned Ground Shields for
               Si-Based RF IC's
               C.P. Yue and S.S. Wong
               Stanford Univ., USA
  15:40  12-2  A 2.7 Volt CMOS Broadband Low Noise Amplifier
               J. Janssens, M. Steyaert and H. Miyakawa*
               Katholieke Univ. Leuven, Belgium and *Toshiba, Japan
  16:05  12-3  A Very Low Offset 1.9-GHz Si Mixer for Direct Conversion
               Receivers
               S. Otaka, T. Yamaji, R. Fujimoto and H. Tanimoto
               Toshiba, Japan
  16:30  12-4  A 2V 1.9GHz Si Down-Mixer with LC Phase Shifter
               H. Komurasaki, H. Sato, N. Sasaki and T. Miki
               Mitsubishi Electric, Japan
  16:55  12-5  A Linearization Technique for CMOS RF Power Amplifiers
               S. Tanaka, F. Behbahani and A.A. Abidi
               UC Los Angeles, USA

                           (Dinner 18:00 - 20:00)

                              Saturday, June 14

 Session 13: Low Power Design [Shunju I]
 Chairpersons:T. Kuroda, Toshiba
              R. Brodersen, UC Berkeley

  8:30   13-1 A Lean-Power Gigascale LSI Using Hierarchical VBB Routing
              Scheme with Frequency Adaptive VT CMOS
              H. Mizuno, M. Miyazaki, K. Ishibashi, Y. Nakagome and T.
              Nagano
              Hitachi, Japan
  8:55   13-2 A Reduced Clock-Swing Flip-Flop(RCSFF) for 63% Clock Power
              Reduction
              H. Kawaguchi and T. Sakurai
              Univ. of Tokyo, Japan
  9:20   13-3 A Lean Power Management Technique:
              The Lowest Power Consumption for the Given Operating Speed of
              LSIs
              S. Sakiyama, H. Nakahira, M. Fukuda, A. Yamamoto, M.
              Kinoshita, A. Matsuzaw a, H. Yamamoto*, Y. Kato*, Y.
              Matsuya**, S. Mutoh**, H. Fukuda**, Y. Nishino ** and T.
              Sakurai**
              Matsushita Electric, *Matsushita Electronics and **NTT, Japan
  9:45   13-4 A Data-Transition Look-Ahead DFF Circuit for Statistical
              Reduction in Power Consumption
              M. Nogawa and Y. Ohtomo
              NTT, Japan

                            (Break 10:10-10:30)

 Session 14: High Speed DRAM [Shunju II]
 Chairpersons:Y. Nakagome, Hitachi
              D. Scott, Texas Instruments

  8:30   14-1 A 1Gbit SDRAM with an Independent Sub-Array Controlled Scheme
              and a Hierarchical Decoding Scheme
              K.-C. Lee, H. Yoon, S.-B. Lee, J.-H. Lee, B.-S. Moon, K.-Y.
              Kim, C.-H. Kim and S.-I. Cho
              Samsung Electronics, Korea
  8:55   14-2 400MHz Random Column Operating SDRAM Techniques with Self
              Skew Compensation
              T. Hamamoto, M. Tsukude and K. Arimoto
              Mitsubishi Electric, Japan
  9:20   14-3 All-Digital Multi-Phase Delay Locked Loop for Internal Timing
              Generation in Embedded and/or High-Speed DRAMs
              K. Gotoh, S. Wakayama, M. Saito, J. Ogawa, H. Tamura, Y.
              Okajima* and M. Taguchi*
              Fujitsu Labs. and *Fujitsu, Japan
  9:45   14-4 A 10ps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock
              Generator Based on an Interleaved Synchronous Mirror Delay
              Scheme
              T. Saeki, H. Nakamura and J. Shimizu
              NEC, Japan

                            (Break 10:10-10:30)

 Session 15: Wireless ICs [Shunju II]
 Chairpersons:K. Yamamoto, Oki Electric
              A. A. Abidi, UC Los Angeles

 10:30   15-1 A 950MHz Second-Order Integrated LC Bandpass Delta-Sigma
              Modulator
              W. Gao and W.M. Snelgrove
              Carleton Univ., Canada
 10:55   15-2 A 900-MHz CMOS Direct Conversion Receiver
              B. Razavi
              Hewlett-Packard Labs., USA
 11:20   15-3 A CMOS Implementation of CDMA/FM IF Signal Processor
              O. Kim, C.-J. Oh, J.-K. Kwon, J.-R. Lee, Q.-S. Song, W. Song,
              K.-S. Kim and H.-M. Park
              ETRI, Korea
 11:45   15-4 A 75mW 128MHz DS-CDMA Baseband Correlator for High-Speed
              Wireless Applications
              K. Onodera and P.R. Gray
              UC Berkeley, USA

                              (12:10 Closing)

 Session 16: Filter and I/O Circuits [Shunju II]
 Chairpersons:N. Lu, Etron Technology
              G. Nasserbakht, Texas Instruments

 10:30   16-1 Dynamic Dielectric Protection for I/O Circuits Fabricated in
              a 2.5V CMOS Technology Interfacing to a 3.3V LVTTL Bus
              J. Connor, D. Evans, G. Braceras, J. Sousa, W.W. Abadeer, S.
              Hall and M. Robillard
              IBM, USA
 10:55   16-2 1 Gb/s Current-Mode Bidirectional I/O Buffer
              J.-Y. Sim, H.-J. Park and S.-I. Cho*
              Pohang Univ. of Science & Technology and *Samsung
              Electronics, Korea
 11:20   16-3 Self-Adjusting Bit-Precision for Low-Power Digital Filters
              P. Larsson and C.J. Nicol
              Lucent Technology Bell Labs., USA

                              (11:45 Closing)
========================================================================