🚀 go-pugleaf

No time to SPICE it, but here is something that works for me.  Device sizes
not included - there is a tradeoff between speed, standing current, threshold
accuracy, and size that requires lots of calculation and SPICEing.  If you
want the details filled in, my fees are reasonable ;-).

Essentially an offset comparator with source followers:

;------------------------------------------------------------------------
; source followers - make M1 stronger, so ( V(1) = V(2) when IN=0.4 )

M1  VSS  IN    1    VDD  PMOS   
M2  VSS  VSS   2    VDD  PMOS      ; node 2 is static

; source follower current mirror:

M3  1    2     VDD  VDD  PMOS
M4  2    2     VDD  VDD  PMOS

; comparator:

M5  3    1     VSS  VSS  NMOS
M6  4    2     VSS  VSS  NMOS

; comparator current mirror:

M7  4    4     VDD VDD   PMOS   ; node 4 is static
M8  3    4     VDD VDD   PMOS

;  output is node 3 - for clean response, add a few more inverter stages
;------------------------------------------------------------------------

With proper device choice, the threshold is a constant times (VDD-2*VT).
Fairly process independent.  Use a stable process like the TSMC 1.2 micron
process, and you can nail the threshold down within a few tens of millivolts.

This can be tailored to any given threshold voltage less than VDD-2*VT, 
including voltages below VSS (hard to design a protection device for that,
though).

The bias rails 2 and 4 can be shared with many inputs to reduce standing
current.  This circuit DOES draw static current.  There are some devices to
peak high speed response which are left out for clarity (and competitive 
advantage).

A fun problem!  It was pretty time consuming the first time I did it on a
customer's circuit, but now it's in the toolkit.

-- 
Keith Lofstrom         keithl@klic.rain.com       Voice (503)-520-1993
KLIC --- Keith Lofstrom Integrated Circuits --- "Your Ideas in Silicon"
Design Contracting in Bipolar and CMOS - Analog, Digital, and Power ICs